TAS6684-Q1: SDOUT Timing

Hi Matthias

The SDOUT follows the same requirement with SDIN, there's only data set-up time and data hold time requirement in the datasheet.

Hi Shadow,

thanks for your reply.

I am confused. I've never come across setup and hold time requirements for outputs and the definition of "requirements" with given minimum values for an output does not make sense to me either. Since there is no timing diagram in the datasheet which would clarify things, the numbers are rather ambiguous.

I would expect something like min,max delays for an output.

So assuming that the setup and hold times for the SDIN input are to be applied to the SDOUT output too, how exactly does that translate to the timing in reality?

So does tDS=8ns mean that SDOUT may toggle at the earliest 8ns before the launch (falling) clock edge?
And does tDH=8ns mean that SDOUT may toogle 8ns at the latest after the launch (falling) clock edge?

Thanks a lot for clarification.

Best regards,

Matthias

Hi Shadow,

thank you for the diagram. I assume tDS and tDH are max values when applied to SDOUT - correct?

Hi Matthias

Matthias Häfner said:

thank you for the diagram. I assume tDS and tDH are max values when applied to SDOUT - correct?

Maybe not necessary? Why would be max value?

Because if these were minimum values, it would mean that SDOUT definitely does not toggle within the window from 8ns before to 8ns after the reference clock edge. 

Ok - that may be the case, but to me, that is a very strange behavior.

Furthermore, without a max-delay specification, SDOUT could toggle outside that window at any time (or not toggle at all -> infinite delay). I am pretty sure that is not how the interface is designed to work.

Hi Matthias

Matthias Häfner said:

Because if these were minimum values, it would mean that SDOUT definitely does not toggle within the window from 8ns before to 8ns after the reference clock edge. 

The 8ns means the data need to hold unchanged during rising edge of SCLK. At least 8ns before or after the rising edge.

Matthias Häfner said:

Furthermore, without a max-delay specification, SDOUT could toggle outside that window at any time (or not toggle at all -> infinite delay). I am pretty sure that is not how the interface is designed to work.

For standard design, Data would toggle at the falling edge of SCLK. So as our amp.

Hi Shadow,

let me repeat my question from the very beginning.

Does tDS=8ns mean that SDOUT may toggle at the earliest 8ns before the falling clock edge?
Does tDH=8ns mean that SDOUT may toogle 8ns at the latest after the falling clock edge?

Hi Matthias

You are describing a very strict requirement, that only ±8ns based on falling edge. It's not necessary.

The datasheet Min value 8ns is based on rising edge as the picture shows. Which gives a forbidden area ±8ns based on rising edge, and all of other area is acceptable.

If still with your method of description, you first should know what is the duty cycle of SCLK, than based on falling edge, limitation would be ±(1/2Cycle-8ns), this time is Max value of limitation.

Hi Shadow,

I am designing a CPLD-based TDM-interface and for that need to know the worst case delays of the amps SDOUT relative to the launch clock edge to ensure timing closure.
When you define SDOUT-timing relative to rising-edge even though the launch edge is the falling edge, it means that the output-delay is dependent on the time between falling end rising clock edge (i.e. clock frequency). And I am damn sure, that is not the case.

Since apparently you don't know these delays, it seems like I have will to measure it myself for my whole operation temperature range and have to put a great safety margin on top.

Maybe you should consult your digital people on how to properly specify a serial interface.