INA 129 PCB layout

Hello Rony,

Thank you for your patience.  In order to minimize noise, first ensure that the supply is low-noise.  For example, you may want to use an LDO to supply the INA.  In addition, be sure to place the power-supply bypass capacitors as close to the supply pins as possible.  With respect to the input traces, be sure to surround the traces (on the same layer and below) with a ground pour.  As you mentioned, filtering the inputs is also recommended.  You can implement both common-mode and differential-mode filters.  The INA149EVM user's guide gives the cutoff equations for such filters.  You may be interested in using an X2Y(tm) capacitor for the input filter.

The tolerance of the internal 24.7kohm feedback resistors is included in the gain error specification.  These resistors are trimmed to absolute values.  That said, it's important to understand why the GE specification changes with increasing gain.  At low gain (e.g. G=1 where Rg=open), the gain error specification is due to the output stage of the instrumentation amplifier (aka the difference amplifier).

As the gain increases (and Rg decreases), the input stage quickly dominates the gain error.  For example, at G=10, 90% of the gain error will be due to the input stage.  At very high gains, however, the gain-setting resistor decreases to a point where wirebonds, interconnects, external connections, and testing limitation become factors.  Therefore, to get a general idea of the tolerance of the feedback resistors we need a non-unity gain specification that has a sufficiently large Rg so as to minimize the affect of the aforementioned 'parasitics'.  I would recommend looking at the G=10 specification for the resistor tolerance (+/- 0.02% typical).

With respect to TC you'll notice that at G=1, the TC=+/-10ppm/C(max).  Remember, at G=1 the error is mostly due to the output stage.  As the gain increases, the TC of the input stage feedback resistors will dominate, hence a separate specification for those resistors in the datasheet.

Hello Rony,

I thought you were interested in low-noise PCB layout suggestions.  Pouring a ground plane that surrounds the signals lowers the impedance to ground, which will allow noise to couple to the ground plane instead of the input signals.  It also will minimize PCB loops that act as antennas.  On thing I should additionally mention is for low-noise layout the use of balanced traces and differential signaling (if possible) is recommended.

Comparing the INA129 and AD8220 is not recommended for they are not similar products.  The AD8220 is a JFET input device, which is more similar to our INA116 than the INA129.  The INA129 is more of a general-purpose instrumentation amplifier.  For example, the INA129 (depending on grade) will draw as much as +/-10nA of input bias current.  The INA116 (JFET input), however, will draw a maximum (depending on grade) of +/-100fA (typical is merely +/-3fA).  The AD8220 has a max input bias current of 25pA, depending on grade.  Their recommendations are valid for minimizing leakage current, thereby preserving the low input bias current of the JFET device. 

To this point we have been discussing general guidelines for PCB layout for I do not fully understand what problem you’re trying to solve.  Please give us additional details and clarify your application so we can give more specific recommendations.  For example you state that your “…application (has) a floating ground similar to the thermocouple apps you have shown in your datasheet…”.  First, can you please be more specific as to the thermocouple application figure that depicts different grounds?  Also, the application is apparently not temperature sensing…so what is the sensor?  Why does it have a different ground connection?  What is the relationship between the grounds?  You also state that an RC filter has been employed…so can you please post your schematic and existing PCB layout?  Please be sure to include all component values.  Also, what is the environment?