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OPA350: DM and CM filter design for current measurement

Chetan Kumar
Prodigy 10 points

Part Number: OPA350

When designing differential‑mode (DM) and common‑mode (CM) input filters for a current‑sense amplifier in a BLDC motor control application, how should the cutoff frequencies be chosen?

Should the selection be based primarily on:

  1. The current‑control loop bandwidth,
  2. The PWM switching ripple frequency, or
  3. The ADC/current‑measurement sampling frequency?

Additionally, are there TI guidelines or recommended practices for balancing ripple rejection with maintaining accurate and fast current feedback for the FOC/BLDC control loop?

  • 0
    TI__Mastermind 30286 points

    Hi Chetan,

    Thank you for your question! 

    For low side current sensing, the phase currents only flow through the shunt resistors when the low side FETs are on. Lets take one of the most challenging cases for low side current sampling and use that to analyze how the CSA input filtering should be designed: At a particular point in the FOC commutation cycle, lets say the duty cycle for one phase is 95% at 20kHz. This corresponds to a low side on time of around 2.5us, though this is actually a little less due to accounting for switching times and deadtime. For most of the period, we have no current flowing through our low side shunt. Once the low side FET turns on for around 2.5us, the phase current now is flowing through the low side shunt, allowing us to measure the phase current to be used in the control loop. In order to measure the current at  high duty cycles, it is important that the filtering frequency of the input filter is not set too low, causing this brief window to get filtered out. The main element that is good to filter out is the switching noise that can be introduced. Another factor that must be accounted for: CSAs have output settling times, so it is critical to ensure that sufficient time is given to allow the CSA output to settle before sampling. Typically this is around 1us. I would recommend an input filter with a cutoff frequency corresponding to no longer than 0.5us-1us to provide decent filtering on the inputs while also not requiring too long of a time before you can sample the CSAs and still get valid information. The longer it takes for the input signal to settle along with the output of the amplifier to settle, the larger the minimum low side on time will be where you can get accurate information.

    Note: For 3 shunt, it is possible to use the other two currents to reconstruct the third current when the low side on time is too small for a particular phase.

    Many customers prefer down up counter mode for PWM generation to allow for center aligned low side current sampling. This is a method that works well for 3 shunt current sensing. It is important to offset the ADC sampling point appropriately to account for deadtime and slew time and to discard any values that are invalid due to too small low side on times.

    Regards,

    Anthony Lodi