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LMH6882 register address error?

Mike Pooley
Prodigy 50 points
Other Parts Discussed in Thread: LMH6882

I have just implemented an FPGA SPI interface to an LMH6882 on an evaluation board. My first verification test was to read the register contents as listed in Table 5 of the datasheet. Most were as listed but the value for register 2 was 3 (decimal) and register 5 was 0. It looked like these were swapped. I have checked the bit stream on an analyser and I am correctly addressing the registers, assuming A3 is the most significant address and A0 the least. Address 2 is 0010 and 5 is 0101 so this is not a direct bit inversion and the other addresses are working correctly.

The default settings for the Power Control and Channel Control registers are as I need and I am able to adjust the gain settings so I believe my interface is working.

Is there an error in Table 5? Should Register 2 be the 'Channel Control' default value 3 and Register 5 be the 'Power Control' deault value 0?

 

  • 0
    TI__Genius 13935 points

    Hello Mike,

    I just pulled up the original design specifications for this part.  Register 5 is the  channel control  and had a default value of 03 (0011). This setting lets channel A and B be controlled separately and immediately updates the gain as the register is updated.

    Register #2 is the power control channel and also had an original default value of 03  (0011). 

    After the original design document was written there was a change in the function of the Power control register.  The two least significant bits of the power control register have no function at this time and it's possible that the default value was changed in a metal edit.  I don't have access to the full design database to check.

    Because the two LSBs in that register have no function the value that they read back is irrelevant to normal device operation, so this should be fine. 

  • 0 in reply to Loren Siebert 1
    TI__Genius 13935 points

    To continue.  If register 5 is loaded with 0 (0000) then updates to the attenuation registers should not be showing up in the actual gain setting. This register was designed to allow for simultaneous updates of the two channels. 

    The first method is to set the #5 register to 4(0100) which will use the A register value for both channels. 

    The second method is to  set the #5 register to 0(0000), load register A, Load register B and then set the #5 register to 3(0011) at which time both channels update to their respective gains. 

    If you do have difficulties go ahead and update this thread and I can help debug them.