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XTR111 EF Operation and 0 - 0.1mA Specifications

Collin Wells
Guru 62035 points
Other Parts Discussed in Thread: XTR111

Collin,

 

My customer Hollysys use XTR111 to build 8 channel V/I circuit. However, the engineer would like to know some of the details specifications.

  1. In datasheet, it guarantee  0.1mA to 25mA performance, however, Hollysys wants to know maximum unadjusted error in 0~0.1mA output.
  2. As for EF pin on XTR111,it is said error detection valid when  wire break, high load resistor, or loss of headroom for the current output to the positive

Supply issued. However, we cann’t find the exactly threshold of different situations, esp. for load resistor. Loss headroom for current output.

Pls advise the trigging level at different situations.

Regards

Hawk Tong

  • 0
    TI__Guru 62035 points

    Hi Hawk,

    Thank you for supporting Hollysys and promoting the XTR111.  That said, please post customer questions to the internal E2E forum to ensure that the customer receives the fastest response time.  I’m going to post this one for you but please post them yourself next time.

    1.)     The specification for the 0mA – 0.1mA range is not specified because the performance in that range is highly dependent on the specifications of the external PMOS transistor that the customer selects.  Basically as the XTR111 attempts to “turn OFF” the PMOS there will be some residual leakage current as well as a minimum output current because the XTR111 can’t drive the VG signal completely to the positive rail which is required to make the VGS voltage 0V which would completely turn the PMOS off.

    2.)    The /EF flag becomes active (pulls LOW) any time the desired output current can no longer be realized due to any of the reasons you’ve listed.  The circuit will operate properly as long as the voltage developed by the load does not reduce the drain-to-source voltage of the PMOS device to the point that forces it out of the saturated (active) operating region ( |Vds| < |Vds(sat)| ).  The maximum voltage on the source of the FET is controlled by the limits of the “IS” pin which are listed versus output current and ambient temperature in Figures 17 and 18 of the datasheet.  From there you’ll combine the IS voltage with the minimum Vds voltage specified for the FET to determine the maximum voltage from the positive supply that will still allow the circuit to operate with the desired current flowing.  If the calculated voltage is exceeded by the load then the FET will begin to get cutoff and the proper current will no longer be able to flow resulting in the /EF flag going LOW.

    Here are some related E2E forum posts that were found by searching for “XTR111 EF”

    http://e2e.ti.com/support/amplifiers/precision_amplifiers/f/14/t/293934.aspx

    https://e2e.ti.com/support/amplifiers/precision_amplifiers/int-precision_amplifiers/f/16/t/126764.aspx

    http://e2e.ti.com/support/amplifiers/precision_amplifiers/f/14/t/316575.aspx