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Power down mode of OPA2836

Trying to verify the power down mode (unity gain) of the OPA 2836, I came up with a problem. I expected to find the output in high impedance state, as it referred in data sheet. Nonetheless I found violations on maximum differential input voltage and maximum continuous input current and I wonder if I have to consider it in power down mode. In more details:

  • Supply voltage: 5VDC, unity gain non inverting topology, non inverting input connected through 560R to ground, output connected through 470R to +5V:

Measured: 1.62V on non inverting input (input current: 2.89mA), 3.69V on output (differential input voltage: 2.07V).

  • Supply voltage: 5VDC, unity gain non inverting topology, non inverting input connected through 560R to 4V, output connected through 470R to ground:

Measured: 2.87V on non inverting input (input current: 5,12mA), 0.95V on output (differential input voltage: 1.92V).

  • Hello, I have forwarded your issue to the product designer to see if he understands why we have such a large differential input voltage. I tried this circuit in TINA and it does show a large differential input voltage compared to what you see in your test. What is the current being consumed by the part in power down mode? Also, is it possible to increase the 470 Ohm resistor on the output? This would greatly reduce the input current that needs to pass through the parts.
    -Samir
  • Hello,
    After looking into the inner design of the part, the 2V differential input makes sense. When the device is in power down, then the current path becomes; 5V supply to 470Ohm to Vout. Vout is shorted to inverting input (buffer config). The inverting input to non-inverting input connection goes through around 40Ohms of base resistance and 2 diode drops. The non-inverting input is then connected to GND through the 560Ohm resistor.
    As far as reliability, the real issue is the continuous input current. In order to reduce parasitics some of the traces in the opamp were optimized for their current-carrying capability. They will be unable to handle 2mA of current. Doing this could cause long term, irreversible damage.
    I would recommend increasing the resistance on the output or non-inverting pin to limit the amount of current.
  • Hello Samir,
    Thank you for your immediate response. Your answer was very helpful. Actually I have a more complicated design. I have nine (9) op-amps with their inputs tied together to a resistor of 560R, which is connected to the output of an DAC (0 – 5V). I have done that in order to exercise the TTL inputs of a UUT (Unit under Test) and log the VIH and VIL of them. But I have also connected nine digital I/Os (tristate capability) to the same points (op-amps outputs) in order to do the digital tests for the UUT. My understanding of Datasheet was that the behavior of the op-amps would be similar to the behavior of a digital tristate buffer and I could isolate the op-amps during digital tests. In actual design, when the op-amps are in power down mode, the output of a single digital I/O is affected by the state of the other eight (8) outputs (through the path: output1-input1-input2-output2…..). So I have to redesign it considering the maximum current.
    Thank you again.