Setup and hold time of PGA870

Muramatsu-san,

To answer your questions:

Q1) In case no latch Mode, What value  ns does it need to fix internal Gain after changing worst gain bit pin?

Ans: The spec for digital pins to propagate internally to fix internal gain or tLATENCY is typically 6.4ns. Once the digital codes are set, it takes a minimum time of 5ns for the gain at the output to settle to the correct gain settings. So, I would think the typical time required for the gain to transition in no latch mode from the time when the digital pins are at the correct logic level to the output settling at the correct gain settings is 11.4ns. This condition is assuming that all the digital pins in no latch mode are at the correct logic levels for a particular gain setting.

Q2) I think gain settling time means reliable output after fixing internal gains,is it correct?

Ans: Yes, the gain settling time means reliable output after fixing the internal gains.

Q3)In case edge triggered mode,What value ns maximum tSU and tHOLD and tLATENCY?

Ans: For the edge triggered mode, the setup time, hold time and tLATENCY are as given in the Digital Inputs table in the datasheet.

Best Regards,

Rohit

Rohit-san

Very thanks for your reply.

And sorry to late reply because I had a vacation and business trip.

Sorry,I didn't inform you enough information.

Our customer ask us worst setup time and hold time.

We checked typical data is in datasheed,but There are no maximum time data.

I changed their questions.

If TI can't garant it ,please inform simulation value or reference value.

Q1) In case no latch Mode, What maximum time value  ns does it need to fix internal Gain after changing worst gain bit pin? I found worst settling time is 20nS in E2E. I need maximum propagate internally information.

Q2)closed

Q3)In case edge triggered mode,What value ns are they maximum time of tSU/tHOLD/tLATENCY?

Regards,

Shinya Muramatsu.