Hello,
We are planning to use the INA206. However, we are a bit confused what is meant by "latch" in the data sheet? The follow is from the datasheet.
The INA206, INA207, and INA208 devices to a maximum of 1.2V when given sufficient time
incorporate two open-drain comparators. These (twice the value of the delay specified for CDELAY).
comparators typically have 2mV of offset and a 1.3μs This entire sequence is reversed when the
(typical) response time. The output of Comparator 1 comparator outputs go low, so that returning to low
latches and is reset through the CMP1 RESET pin, exhibits the same delay.
as shown in Figure 35.
Based on that, I'd expect to be able to latch the comparator output high or low by using the RESETn pin. However, looking at figure 35, I don't see how the RESETn pin actually works. It seems like it doesn't have much impact on the comparator output. It looks like there is a delay when Vin goes below 0.6V, but I'm not making sense of it. I'm sure I'm missing something. Could you clarify?
Thank you