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INA206 RESETn latch

Other Parts Discussed in Thread: INA206, INA208, INA207

Hello,

We are planning to use the INA206.   However, we are a bit confused what is meant by "latch" in the data sheet?  The follow is from the datasheet.

The INA206, INA207, and INA208 devices to a maximum of 1.2V when given sufficient time
incorporate two open-drain comparators. These (twice the value of the delay specified for CDELAY).
comparators typically have 2mV of offset and a 1.3μs This entire sequence is reversed when the
(typical) response time. The output of Comparator 1 comparator outputs go low, so that returning to low
latches and is reset through the CMP1 RESET pin, exhibits the same delay.
as shown in Figure 35. 

Based on that, I'd expect to be able to latch the comparator output high or low by using the RESETn pin.  However, looking at figure 35, I don't see how the RESETn pin actually works.  It seems like it doesn't have much impact on the comparator output. It looks like there is a delay when Vin goes below 0.6V, but I'm not making sense of it.  I'm sure I'm missing something.  Could you clarify?

Thank you

  • Jamaal,

    First, the drawing in figure 35 is a drawing, so if the edges don't line up perfectly, that's possible.

    Second, I put figure 35 below with numbers on the transitions so I can explain them.

    1. reset high, VIN exceeds limit, CMPout goes high.

    2. reset goes low while CMPout still exceeds limit, so no change.  So long as the limit is exceeded, in either mode, CMPout stays high.

    3.VIN falls below limit, but since reset is still high, CMPout doesn't change.

    4. With VIN below limit, CMPout falls when reset falls because the output latch is being reset to low.

    5. Same as 1.

    6. Same as 2, but now reset is held low.

    7. Because reset is low, when VIN drops below limit, CMPout resets low immediately.

    8 and 9. CMPout follows VIN high and low as VIN exceeds the limit.

    Basically, if reset is high and VIN exceeds the limit, CMPout stays high until VIN is below the limit AND reset is issued at that time.

    If reset is low, CMPout follows VIN as it exceeds and falls below the limit as it happens.

    Adding a capacitor to increase delay makes the CMPout lag behind VIN exceeding the limit voltage, shifting the CMPout wave to the right.

  • Thank you Jason,

    That is very helpful. Just to verify how we will use this in our application. If RESET = HI:

    The user will normally access the INA206 at comparator out.

    (1) You write “if reset is high and VIN exceeds the limit, CMPout stays high until
    VIN is below the limit AND reset is issued at that time.” Now pin 6 is open-drain
    so a pull-up is called for. Does your statement really refer to point “x”?
    This would be pin 6 tied to a pull-up.

    That is, is it more correct to say “if VSNS > VTRIP then point “x” = HI”?

    (2) Keeping RESET = HI, you write “if reset is high and VIN exceeds the limit,
    CMPout stays high until VIN is below the limit AND reset is issued at that time.”
    What does “reset is issued” mean? Does it mean power is toggled on/off?
    The RESET pin is toggled LO? Or what?

    (3) Again w RESET = HI, for the INA206 there are two comparators and a window comparator
    can be configured (data sheet Fig 41)

    When you write “if reset is high and VIN exceeds the limit, CMPout stays high until
    VIN is below the limit AND reset is issued at that time” does this apply to both VUPR and VLWR?

    That is, is point “x” = HI for BOTH cases: (1) when VIN > VUPR (shown in RED)
    and (2) when VIN < VLWR (shown in GRN)? This is important for me to know.

    In other words is point “x” = HI both when VIN rises ABOVE VUPR and in the case when VIN falls BELOW VLWR?

    Thank you
  • Hi Jamaal,
    Is there a attachment that you are referering to. Can you please retry attaching.
  • Sorry,

    Moving too fast.  "x" is the comparator output.

    Thanks

  • Hi Jamaal,
    (1) For Comparator 1: RESET = high, Vin exceeds the limit CMPOUT = high and stays high until Vin is lower than limit and RESET = low. You can tie a pull up to reset and pull it low when needed or it can be directly switched between supply and ground as shown in figure 30.
    RESET = low, Vin exceeds the limit CMPOUT = high and when Vin is lower than the limit CMPOUT = low. It's basically like a transparent mode.
    (2) RESET = High means tie it to supply and RESET = low means tie it to ground.
    (3) This is my undestanding:
    Reset = low and when VIN < lower window voltage or when VIN > upper window voltage, the COMPOUT = Low and
    when VIN is within lower and upper window voltage COMPOUT = high.
    When Reset = high and Vin is within the upper and lower window voltage then COMPOUT = high and output will remain high for the case VIN < lower window voltage but COMPOUT = low for the case VIN > upper window voltage since the comparator 2 pulls the output low. So I think Reset should be low for the window comparator to work correctly.
    But let me verify this and get back to you tomorrow.
  • Thanks Rabab,

    A couple things to clarify, sorry...

    (A)RESET = high, Vin exceeds the limit CMPOUT = high and stays high until Vin is lower than limit and RESET = low.

    You can tie a pull up to reset and pull it low when needed or it can be directly switched between supply and ground as shown in figure 30.

     

    Let the circuit be such that RESET = CMPOUT = HI 

    OK, so given this circuit arrangement clearing a fault (in other words, to clear CMPOUT) requires TWO conditions: (a) VCMP_IN > 0.6V AND (b) RESET must go LO.

    The data sheet on page 6: “Comparator Power-on Reset Threshold = 1.5V”

    “The comparator will be in reset as long as the power supply is below the voltage shown here. If CMP1 RESET is high at power-up, the comparator output comes up high and requires a reset to assume a low state, if appropriate.”


    Our complication with that...we must manually assert RESET = GND at power-up at power-up, say, (or else CMPOUT will never be cleared)?

    (B)When Reset = high and Vin is within the upper and lower window voltage then COMPOUT = high and output will remain high for the case VIN < lower window voltage but COMPOUT = low for the case VIN > upper window voltage since the comparator 2 pulls the output low. So I think Reset should be low for the window comparator to work correctly.  But let me verify this and get back to you tomorrow.

    If I correctly understand you I hope that this is NOT the way the INA20x window comparator works.  I would hope that for the VUPPER fault the VIN value would be such that VCMP_IN > (greater than) 0.6V (as just described above) but for the VLOWER fault VIN is such that VCMP_IN < (less than) 0.6V.

    Thanks,

    Eric

  • Hi Jamaal,
    Clearing CMPOUT = HIGH when RESET = HIGH to CMPOUT = LOW will require Vcmpin+ < 0.6 and RESET = LOW (if using the internal 0.6 V reference). This is only applicable to comparator 1. Comparator 2 doesn't have the reset option.
    Your understanding is correct regarding the "Comparator Power-on reset". If RESET = HIGH at power up COMPOUT = HIGH and will need RESET = LOW as long as the input is below the limit.
    To answer the window comparator question, I need some info. Are you using the 10 pin device or the 14 pin. What are your Vupper limit and Vlower limit and how are you setting it.
  • Thanks Rabab,

    I am using the 10-pin device.  Here is my circuit:

     

    The circuitry hanging on the RESET pin just keeps RESET = LO for ~100ms after power up.

     

    Here is how I have set VUPR and VLWR:

    I want VSNS ~ 200mV (see INA206 data sheet Fig 6).

    So I*(Ω)·RSNS(A) = 0.2V.

                                            For VUPR choose I* = 3A

    RSNS = 0.2V/3A = 0.067Ω (here I’ve used two 0.13Ω resistors in parallel).

    VSNS = 3A·0.065Ω = 0.195V (almost 200mV).

    INA206 has G=20 so G·VSNS = 3.9V.  This is VUPR.

    Now divide G·VSNS = 3.9V down to 0.6V.  The 10K-1.82K divider does this.

    Fig 41 in the INA206 data sheet associates VUPR with VCMP2IN so I’ve connected VUPR accordingly.  This is how VUPR becomes VCMP2IN.

                                            For VLWR choose I* = 1A

    RSNS = same, of course = 0.067Ω .

    VSNS = 1A·0.065Ω = 0.065V (not even close to 200mV!).

    Here G·VSNS = 1.3V.  This is VLWR.

    Divide G·VSNS = 1.3V down to 0.6V.  The 10K-8.06K divider does this.

    Fig 41 in the INA206 data sheet associates VLWR with VCMP1IN so I’ve connected VLWR accordingly.  This is how VLWR becomes VCMP1IN.

    Thank you

  • Hi Jamaal,

    I noticed in your schematic that you do not tie the CMP1 and CMP2 outputs together. I do not think you can use them as a wndow comparator without conecting them. You have configured them as separate comparators. These will be the results:

     0<OUTPUT< 1.3 V, CMP1OUT = 0 and CMP2OUT = 1

    1.3 V < OUTPUT < 3.9 V, CMP1OUT = 1 and CMP2OUT = 1

    OUTPUT > 3.9 V, CMP1OUT = 1 and CMP2OUT = 0

    Have you built this prototype?

     

  • Hi Jamaal,
    This is a follow up to the email. As long as Reset is set low, INA206 will work as a window comparator. If the reset is high then it will only work as a upper limit comparator.