LMH6881 Power ON Status at Serial Mode

Masaharu Katayama

Other Parts Discussed in Thread: LMH6881

Dear Sir,

LMH6881 sometimes keeps Amp Power Off situation after Vcc powering up under Serial Mode (SPI Compatible) until writing Register 2 to power on.

Pin connections are as follows;

SPI pin : directly connected to Vcc

SDO(D0) pin : Open

SDI(D1) pin : Lo level input / FPGA

CLK(D2) pin : Lo level input / FPGA

CS(D3) pin : Lo level input / FPGA

SD pin : connect to GND through 270ohm

As SDO is open (not use read-back by FPGA),　then I could not check Register 2 status when the device was power-up.

Questions are;

- Isn't LMH6881 always power on status at powering up under serial mode?

- Abut pin connections, especially above SPI, SDO, SD connections are okay? Is there any suggested connections including unused even disable pin like SD? SPI pin becomes Vcc from zero volt at powering up.

I understand default Register 2 is power ON(0,0) and SD pin is disabled at serial mode.

I expect that the device is always power on status just after powering up at the serial mode.

Best regards,

Masa

over 9 years ago

0 Masaharu Katayama over 9 years ago

Expert 1420 points

May I get somebody's support?

0 Loren Siebert 1 over 9 years ago

TI__Genius 13935 points

Hello Katayama-san,

You are correct, in SPI mode the LMH6881 is supposed to power up with the amplifier active.

When the SPI pin is at a logic 1 state, the SD pin has no function. When the SPI pin is at a logic state 0 the SD pin will turn the amplifier on or off.

In SPI mode the CLK and SDI pins will not matter at first. The CS pin should be at a logic 1 level until it is time to write data to the chip. It should be returned to logic High at the end of the data write operation as shown in FIgure 40.

I do not know kf the CS pin level has any influence on the issue you are seeing with the amplifier being disabled on power up in SPI mode. I will have to investigate this to answer your question.

Best Regards,

Loren

0 Masaharu Katayama over 9 years ago in reply to Loren Siebert 1

Expert 1420 points

Hi Loren,

Thank you very much for your support.

CS is connected to FPGA through digital isolator below.

Power is up VCC1 first, then VCC2. Just after VCC is supplied, FPGA is still in configuration, FPGA IO output is high-Z, then D3/CS is Lo by pull down resistor.

After completion of FPGA configuration, FPGA IO will make D3/CS Hi .

May I get your answer if this was an issue?

Best regards,

Masa

0 Loren Siebert 1 over 9 years ago in reply to Masaharu Katayama

TI__Genius 13935 points

Hello Masa,

Does the SPI pin also have a delay? If the amplifier powers up in parallel mode it could be that the SPI registers do not influence the power on state.

Regards,

Loren

0 Masaharu Katayama over 9 years ago in reply to Loren Siebert 1

Expert 1420 points

Hi Loren,

The SPI pin is directly connect to VCC2 which supply for Amp. So it is expected to be SPI mode at the power on state.

Best reards,

Masa

0 Loren Siebert 1 over 9 years ago in reply to Masaharu Katayama

TI__Genius 13935 points

Hello Masa,

The only thing I can think of that would cause this is that noise on the clock while CS is low is clocking data into the registers.

Is this a critical issue? Is it OK that you can use SPI bus to turn the part back on?

Regards,

Loren

0 Masaharu Katayama over 9 years ago in reply to Loren Siebert 1

Expert 1420 points

Hi Loren,

I would like to make sure if the CS is a cause of the phenomenon. Do you strongly recommend to pull D3/CS up high? I found the EVM schematics pull up with 1.5kohm but no guideline in the datasheet.

Best regards,

Masa

0 Masaharu Katayama over 9 years ago in reply to Masaharu Katayama

Expert 1420 points

Hello Leaon
I would like to hear the recommendation.
Best regards,
Masa

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LMH6881 Power ON Status at Serial Mode