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LMV793 characteristics data request

Kazuya Nakai59
Guru 20945 points
Other Parts Discussed in Thread: LMV793, OPA322

 Hello guys,

 One of our big customer wants to register LMV793 as their company internal official parts to use the device for their many products.

 Also they need the following characteristics data for the registration.

  So could you please give me the following data?

 1. Offset voltage versus common mode voltage characteristic

     The following graph is OPA322's one.

    The customer needs the same graph of LMV793.

   2. What is happen when input voltage (+IN,-IN) of LMV793 is higher than power supply pin (+V) voltage?

      Is there any protection circuit to avoid breaking the device in the condition?

   3. What is the maximum gain of the device?

 Your reply would be appreciated.

 Thank you and best regards,

 Kazuya Nakai.

  • 0
    TI__Genius 13935 points
    Hi Kazuya,

    #1. I will need to look into this to see what we can do.

    #2. Typically Op Amp inputs are not over-voltage protected. The ESD diodes will provide some limited protection, but they are not designed for over voltage conditions. I would recommend not counting on internal protection beyone the ABS MAX numbers. With CMOS devices the failure modes are most likely gate oxide failure.

    #3 I would say that 20dB down from the guaranteed open loop gain is about as much gain as you can successfully use, so that would be 60dB. At that gain you would have very little available bandwidth, distortion performance would be fair to poor and the offset voltage would probably need to be offset. The practical limit to maximum gain is usually the desired bandwidth. From the AOL curve it looks like the bandwidth at 60dB of gain would be 100kHz.

    Regards,
    Loren
  • 0 in reply to Loren Siebert 1
    Guru 20945 points
    Hi Loren,

    Thank you ver much for your reply.
    1. I hope TI has any graph or data like Figure 8 on OPA322 datasheet.

    2. I understood that LMV793 failure mode in case of 0.3V higher input voltage higher than V+ is most likely gate oxide failure.
    But I think 0.3V could be very conservative. Do you know actual voltage breaks input CMOS gate oxide?
    Also I think input terminal has ESD protection diode connect to GND(V-). Is this diode breakdown voltage higher than the gate oxide one?

    3. I understood.

    Thank you very much again and best regards,
    Kazuya Nakai.