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TL3016: Input Overdrive performance

Part Number: TL3016

For some reason, E2E will only let me put this in the High Reliability Forum.  Don't why, seems like a bug, please move as needed.

Our customer is powering the device from +/-5V.  In this particular circuit, during a transient event the inverting terminal could get clamped to one schottky diode drop beyond the power supplies.

Will this cause phase reversal or any other non-ideal behavior?

The non-inverting terminal will within -2V < V+ < +2V.

Also, there is still confusion about the LATCH ENABLE logic.  I see in the old internal forum that the data sheet was going to be updated with this language on the cover sheet,

"The TL3016 is an ultrafast comparator designed to interface directly to TTL logic while operating from either a singe 5-V power supply or dual +/- 5-V supplies.  It featuress extermemly tight offset voltage and high gain for precision applications.  It has complementary outputs that are latched when the LATCH ENABLE input is held high.  For flow through applications, the LATCH ENABLE pin must be held low."

But apparently the data sheet was never revised.

  • Strange, I am not sure why it is associating with the high rel product.  I will see if someone can look into that.

    I will attempt to move post.

    Thanks,

    Wade

  • Hello,

    Comparators that don't have output anti-phase reversal circuitry built in may phase invert if the input level exceeds the maximum common-mode voltage (VCM) limits. The TL3016 datasheet does not make any mention of phase reversal, or internal circuits to prevent it. Also, when I review the intenal schematic it doesn't appear to have the feature built in. Therefore, I do suspect that if the VCM range is exceeded there is the possibility for output phase inversion.

    The output latch is active (hold state) when the latch pin is held high; therefore, for normal output that can change state in reponse to the input levels comparisons the latch pin is held low.

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • Thomas-

    Thanks;

    If VCM defined to be (V,inv + V,non_inv)/2 then worst case VCM = 1/2(+/-2.0 +/- ~5.4) ~= +/-3.7V.

    Page 4 of the data sheet states that -3.75V <= VCM <= 3.5V.

    Please note that in this application one side of the input differential pair will always be held to +/- 2V, and biased properly.

    Could this thing really phase invert if one side of the differential pair is still biased correctly?

    Doesn't phase inversion usually occur when both sides of the input stage gets shut off due to a lack of headroom?

    Thanks, Best, Steve

  • Hi Steve,

    I would say that VCM definition is applicable when the comparator is operated within the specified VCM region. I do suspect the TL3016 may not phase invert with one input in the range of +/-2 V and the other input within a range that includes the supply levels, but TI cannot make assurances because it is not specified in the datasheet. Having an input set to a level beyond the supply level makes it even more difficult to predict.

    Output phase inversion occurs when a transistor in the input differential stage is driven into saturation. In normal operation the collector is voltage swing is inverse to that of the base. However, when the transistor is saturated, the collector moves in phase with the base. The net result is the output is phase inverted from the normal operating mode.

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • Thomas-

    There is an unencrypted SPICE model for the TL3016 online. 

    Do you think it may be sophisticated enough to reveal phase inversion in simulation?

    Best, Steve

  • Hi Steve,

    The TL3016 simulation model is a behavioral model, not an exact replica of the transistor circuit. It will model normal behavior, but not usually something such as output phase inversion unless designed to do so. The documentation I have for the model doesn't indicate it models output phase inversion.

    I tried setting up and simulatiing the circuit as you described with the +5.4 V dc level on one input, and the +/-2 V signal on the other input. The outputs didn't chnage state as would be expected for the ideal case.

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • I also did the same simulation in TINA and had the same result.

    After looking at the model file a bit, it definitely looked behavioral, and assumed it probably wouldn't model inversion well, if at all.

    Any chance we could take a look at the input stage schematic for any clues?

    -Steve