We attempted to assemble a wide-bandwidth multiplier, using your MPY634, but detected that its AFC was boosted with frequency (see table 1). Then we have assembled a test schematic in a prototype board with a MPY634 chip, just received from you (table 2). Results are quite similar. The schematic, used for the tests, is attached. Is any mistake in it?
TABLE 1 |
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F, kHz |
SF(calculated) |
A(X), V |
A(Y), V |
OUT, V |
OUT. (calc) |
15 |
13,921875 |
8,25 |
6,75 |
2 |
2,784375 |
150 |
13,37962963 |
8,5 |
6,8 |
2,16 |
2,89 |
1500 |
3,515625 |
9 |
6,25 |
8 |
2,8125 |
TABLE 2 |
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F, kHz |
SF(calculated) |
A, V |
OFFSET, V |
OUT, V |
20 |
8,964552239 |
1,55 |
0,05 |
0,134 |
100 |
8,704710145 |
1,55 |
0,04 |
0,138 |
300 |
6,76 |
1,56 |
-0,04 |
0,18 |
600 |
3,954222973 |
1,53 |
0,08 |
0,296 |
1000 |
2,098880597 |
1,5 |
0,04 |
0,536 |
1500 |
1,216901408 |
1,44 |
0,04 |
0,852 |
2000 |
0,813616071 |
1,35 |
0,04 |
1,12 |