Dear e2e Team,
In the Figure 4 and 5 of the datasheet the logic presented is:
IN+ bigger thet IN- => Output Q8 open => OUT 5V
IN- bigger thet IN+ => Output Q8 close => OUT 0V
However, In the Figure 13 the logic presentesd is the oposite:
IN- bigger thet IN+ => Output Q8 open => OUT 5V
IN+ bigger thet IN- => Output Q8 close => OUT 0V
If I refer to the section ; 9.2.1.2 Detailed Design Procedure, we might have the circuit below.
And the simulation with TINA TI gives :
But if we have a look at the figure Figure 13 it's the opposite.
The Figure 13 of the datasheet is it correct or there is something I didn't get?
Thank you very much for your help,