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Product Suggestion

Other Parts Discussed in Thread: BUF602, DAC3151, UCC27531, UCC27538

Hello all,

A customer ask,

" I'm looking for an experimental solution to evaluate dynamic adaption of high speed gate drive waveform. While an immediate replacement for proper gate drivers (>= 3A) might not be available, I imagine paralleled buffer ICs might be a starting point. I'm already familiar with BUF602, so my search brought up LMH6321MR/NOPB SO PowerPAD (DDA) BUF634T TO-220 (KC) | 5 as possible candidates. Along with a Lattice MachXO3, DAC3151 and a suitable high speed op-amp this might be sufficient to demonstrate the feasibility. I'd love to hear your suggestions regarding the selection of parts and possible alternatives.

Could anyone help me with this ?

Thank you in advance.

  • Hi Kaustubh - do you have a schematic? If so, can you email it to me? - thanks, Jim
  • Hello Kaustubh,
    While it is possible to create high speed gate drives from discrete op-amps, integrated solutions are more desirable.
    High speed op-amps may appear to work, but when tested or modeled with parasitics the problems will surface.

    At very high dV/dt and di/dt, the parasitic inductance of IC packaging and PCB's will greatly degrade the ability to drive fast slew rates.
    TI's GaN landing page discusses this and many other aspects of high speed power, GaN and SiC.
    www.ti.com/.../gan-overview.page

    Please explore this area on TI.COM
    You will find much useful information.

    TI also makes Mosfet Drivers.
    www.ti.com/.../mosfet-and-igbt-gate-drivers-overview.page
    These are also very fast to meet today's design requirements.

    If you still want to pursue a discrete approach you should quantify:
    - dV/dt of the power stage
    - di/dt of the power stage
    - Power devices being considered, mosfets, GaN, etc.
    This leads to gate charge, turn on/off time, efficiency, speed at which power devices must be turned on/off
    - Switching frequency of the power stage
  • Dear Mr. Walker,

    thanks for the advice. Here's my reply to a previous email.

    ***

    thank you for looking into this. I’ve looked around with the parametric search and we’re now also considering using proper SiC gatedrivers.

     

    Here’s a quick selection of parts that may enable us to control the current waveform utilizing devices in parallel. The idea is to combine two drivers into a tri-stateable secondary driver and connect it in parallel to the primary driver. Either the on-state resistances or combinations of additional gate resistors can thus be used to dynamically control the gate current waveform to within the accumulated jitter of the control paths.

     

    UCC27531 - 2.5-A, 5-A, 35-VMAX VDD FET and IGBT Single Gate Driver

    http://www.ti.com/lit/gpn/ucc27531

    UCC27531DBV IN1, EN

    UCC27538DBV IN1, IN2

     

    Double pulse testing with a IXD609 9A gate drivers  is under way so I can’t quote relevant specs right now but dV/dt in the 50kV/µs region is to be expected.

     

    Unfortunately I cannot login / register right now because the page returns a server error. Have a nice weekend.

     

    Best Regards,

    Helge B. Wurst

     

     

    Ps. In another design we’re supposed to use there are AMC1304 sigma delta modulators used for health status monitoring on the isolated side. It seems like we’ll be having some issues there with the device only being rated for 10kV/µs common mode transients. How would the device perform with transients in excess to that, especially since the clock is supplied externally? Surely we can suppress the bitstream around the transients but a latch-up or failure mode would be counter-productive. I’ve seen some posts in the e2e forums regarding ISO76xx and ISO72xx dV/dt issues and they’re rated for 50-75kV/µs.

    Much obliged for your help.

  • Hello Helge,

    The UCC27531 and UCC27538 provide a VDD operating range suitable for driving SiC devices with the capability up to 35V so these devices are a good choice in this regard. I would suggest a driver and package combination which has the separate high side and low side pins (OUTH and OUTL) to provide more flexibility on source and sink current from each driver.
    There is not the ability however, to tri state the output of the driver. The drive will either be sourcing or sinking current during the time period that you will be staggering the parallel driver stages.