LMV841: Capacitive load and "RISO"

David,

I agree with Kai that 1k Riso resistor in most applications is unnecessary and in case of resistive load results in a large output voltage gain error due to Riso/Rload voltage divider.

You may simulate or test the stability of the circuit by looking at the small-signal (+/-10mV) overshoot directly at the output of the amplifier, Vo.  After measuring the percent overshoot, you may use the graph below to determine the actual phase margin.  The goal is to assure a phase margin of 45 degrees or greater, which correlates with the overshoot of 25% or less - see graph below.

You do not provide any information about the circuit configuration, which plays a major role when it comes to circuit stability - higher close-loop gain typically allows higher capacitive load drive.  Thus, for illustration I'll assume here a worst-case scenario that you attempt to drive 33nF in a buffer configuration.   

 Remember, you must look at the Vo overshoot and not Vout.  Based on the above simulations, you may see that Riso of 100ohm results in the overshoot of (14.4mV-10mV)/20mV*100% = ~20% - this correlates with around 48 degrees phase margin, which assures a stable operation of the circuit over silicon wafer process variations.  I have attached here Tina-TI circuit schematic so may may use it fort your own simulations.

David LMV841.TSC

Thanks. In datasheet for OPA2171 there's a graph that shows result of stability measurements and in that case 1k is fine but not always with huge margins (funny how high capacitance requires lower RISO):

I use LMV84x in various blocks, almost all of them are voltage followers (gain = 1), always followed by a resistor (minimum 1k) and usually a capacitor (usually 33nF but might want up to 47nF). The signals go to SAR ADCs and we usually need to at least prepare for RC links for two reasons: SAR capacitive load and filtering of signal. I might later decide to remove RC link entirely and rely on OP having low enough output impedance to counteract SAR capacitive load (total ADC cap is <30pF so it is within what LMV84x is specified for), but I want possibility in the first version of this board to use either RC link or good OP to fulfill SAR requirements. And I want to be able to guess RISO values that will work so that I won't have to sit and exchange all of them later.

Sounds to me like 1k most probably will work (based on gut feeling even 100 ohms probably has sufficient stability but maybe just barely), and if I want a definite answer before I have the boards the best way is to use the simulation model you provided. I assume model is good enough to incorporate these phenomenons?

BTW if I simulate do I need to look at overshoot (time domain), can't I look directly at the loop (frequency domain)? And is a model available for LMV84x that can be used in 3rd party simulation tools like Pspice?

Hi David,

you wrote:

" In datasheet for OPA2171 there's a graph that shows result of stability measurements and in that case 1k is fine but not always with huge margins (funny how high capacitance requires lower RISO)."

Please have a look at figure 40 of datasheet of OPA2171. You will notice that there are 2k5 input protection resistors:

These two resistors complicate the phase performance because they increase the phase lag in the feedback loop. They also turn currents flowing in the feedback loop into common mode voltages which additionally complicate the phase performance.

I have carried out a simplified (read simplified!) phase stability analysis, which only takes the open loop output impedance, the input protection resistors and the input capacitances of OPA2171 into account. It shows what high impact the protection resistors have on the phase response. First, the case of no input protection resistors is simulated. Load capacitance is 100p:

You see, that you get an additional phase lag in the feedback loop of only about 15° at the unity gain frequency. Now see what happens when the internal protection resistors are added:

The phase lag has considerably increased now. An isolation resistor of 50R would not help much:

Only a much higher isolation resistor would restore the phase margin, at least partially:

Now the situation with a load capacitance of 100n. First without the input protection resistors, then with them added:

In both cases the phase margin is heavily eroded.

Now the same situations with a 50R isolation resistor:

You see that a 50R isolation resistor is sufficient now.

Kai

Thanks. I guess that explains why higher cap load requires lower RISO. Note that I do use both OPA4171 and LMV84x in my design but mostly LMV84x and with OPA4171 I have no questions since all I need is in the datasheet. So this sounds like items of peripheral interest to me, my other questions were of higher importance.

(BTW LMV84x also has resistors at input, R1 and R2 in figure 34 of datasheet, which seem to be only 130 ohms though.)

Hi David,

different capacitive loads affect the phase response at different frequencies. With a load of 100n you have two "construction sites", one at about 100kHz and another at the unity gain frequency due to the internal protection resistors. Then a standard isolation resistance is adequate. But with a load of 100p the two construction sites coincide at the same frequency, the unity gain frequency. Then a much higher isolation resistor is needed.

The LMV841 has much smaller input protection resistors. So, these should have much less impact on the isolation resistor requirements.

By the way, what ADC are we talking about?

Kai

Thanks. ADC is part of microcontroller.

My main questions are these:

Sounds to me like 1k most probably will work (based on gut feeling even 100 ohms probably has sufficient stability but maybe just barely) so I think I can start with mounting that and test when I have the boards. If I want a definite answer before I have the boards the best way is to use the simulation model you provided. I assume model is good enough to incorporate these phenomenons?

BTW if I simulate do I need to look at overshoot (time domain), can't I look directly at the loop (frequency domain)? And is a model available for LMV84x that can be used in 3rd party simulation tools like Pspice?

Hi David,

you can return to us if you have any doubts. :-)

Of course, you can also look at the frequency domain. But then you must do a frequency sweep. It's much easier to check stability by the help of step voltage respsonse, though. By the way, the SAR ADC is also demanding a step response from your OPAmp circuit. Remember that the OPAmp must settle within the data aquisition time.

As an aside, the isolation resistor could be part of a voltage divider at the input of ADC in order to scale the input voltage. I have done this with an ATMEGA328 once. Directly at the ADC I used a 100n cap.

Kai