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TLV2370: Does Sallen-Key filter need a high impedance load?

Part Number: TLV2370
Other Parts Discussed in Thread: LMC6041, OPA130, , TL081

I am using the circuit below to monitor the output of a piezoelectric diaphragm, represented by a sine wave generator and capacitor C3.

The circuit is powered from a split supply (+5V/-5V) derived from a linear power supply (230V, 50Hz). I need the full rail-to-rail dynamic range (or as close as possible).

The functions of the amplifiers are as follows:

  • U1 - charge amplifier, frequency range of interest: 1Hz-60Hz
  • U2 - Sallen Key filter, low pass, fc = 110Hz
  • U3 - scale and bias amplifier to convert U2 output to 0V min, +3V max, suitable for ADC.

The circuit works in simulation, but in practice I find that a high amplitude mechanical impulse on the piezoelectric disk causes U3 to oscillate'. (The signal seems to output narrow pulses which jump to the +5V rail at a frequency of 50Hz). The oscillation will eventually disappear (after about 30-40 seconds) if the piezo is left untouched. I checked the power supply rails - they are clean with little ripple, even when the oscillation is happening.

If I disconnect U3 and monitor the output of U2, the problem does not occur. I can "cure" the oscillation in the circuit by putting a voltage follower amplifier between U2 and U3.

My question is: Does U3 cause a problem for the stability of U2 at high frequencies? The impedance of C101 will be low for a high frequency impulse and U2 is trying to drive current to support this as well as maintaining the correct current through R5 to keep the input voltages on pin 2 at around 1V d.c.

Perhaps there's a better way to offset the output signal?

  • Hi D B17,

    Thanks for contacting the GPAmps group.

    -Could you please post scope shots of the oscillations you described during those 30-40s time frame? What do you mean by "if the piezo is left untouched"?

    -What do you mean by "The circuit works in simulation"? In your simulation, did you use a pulse signal or a sine wave sometimes using a sine wave will show good results when using a pulse would be more accurate. Did you run a phase margin simulation? or what kind of simulation did you run exactly?

    I simulated the 3rd stage of your circuit as shown below and i can observe a very low phase margin at 17.7 which in combination with your first two stages may be the cause of the oscillation. Additionally, notice also the small bandwidth of the 3rd stage which could cause oscillations if your signal at stage 2 is out of bounds. w

    Thanks in advance for clarifying the above concerns. 

    Regards, 

    -Mamadou

  • Hi,

    U1 is a strange circuit: R2 and C3 form high pass with a corner frequency of 160Hz. And R3 and C1 form a low pass with a corner frequency of 0.2Hz...

    Kai
  • Hi Mamadou. Thank you for your quick and full response, I really appreciate it.

    Firstly, just to clarify, capacitor C3 + sine wave generator XFG1 in my diagram are merely a crude representation of the piezoelectric disk at low frequency. In reality, the two terminals of this disk are soldered to one end of a 2m length of coaxial cable. At the other end of the cable, the cable core is connected to R2 and the cable screen is connected to signal ground GND.

    R2 (33K) and the piezo capacitance form a low pass filter of time constant Cp*R2, where Cp is the piezo capacitance (probably about 60nF). I could increase R2 to reduce the filter cut-off but I don't want to attenuate frequencies less than 60Hz. (1/2.pi.R2.Cp = 80Hz at the moment)

    By "the piezo is left untouched", I mean that the piezo disk is laid on a flat surface and is not subject to any mechanical vibration, although it is electrically connected to R2 and signal ground.

    The oscillations seemed to be triggered when the piezo experiences a large mechanical impulse. For example, if the piezo is on a surface that is vibrating sinusoidally at 16Hz, and then I tap it sharply, the circuit will typically output a signal at U3 pin 6 with waveshape shown below (you can see the oscillation superimposed on a 16Hz sine wave):



    If I then turn off the input vibration, the U3 output will continue to oscillate, typically with an output as shown below:



    I'm still at the breadboard stage.....For each op amp, I'm using a 100nF ceramic disk to decouple between +5V & GND and -5V & GND. Plus a 10uF tantalum between +5V & GND where the incoming d.c. supply is connected to the breadboard.

    I am using a program called Multisim to check the operation of the circuit. I did use an a.c. sine wave input sweep to test the gain and phase response. I also varied the sine wave input frequency manually on generator XFG1 and checked that the output was as required. This is what I mean by "the circuit works in simulation". I agree it's not a thorough test and I will look at the impulse response. My version of the Multisim software does not have phase margin capability unfortunately.

    Thank you for checking phase margin for stage three. I'm not familiar with the routines you have used to do this. On your diagram, R5 is connected to ground. Shouldn't R5 be connected to the input signal instead or am I missing something?

    Is there any way I can increase the phase margin for each of the three stages, please? I'm grateful for any comments on the circuit in general.

  • Hello Kai. Thanks for your comment. Indeed, that bandpass filter is what I'm hoping to use to my advantage. I want to detect oscillations in the 1 to 60Hz range only and attenuate all high frequency signals.

    The circuit is described in section 3.2 of Texas Instruments application note SLOA033A
    www.ti.com/.../sloa033a.pdf
    If I've misunderstood this description, would be grateful for your comments!
  • Kai, "U1 is a strange circuit: R2 and C3 form high pass with a corner frequency of 160Hz. And R3 and C1 form a low pass with a corner frequency of 0.2Hz..."

    Isn't it the other way around? R3/C1 form the high pass and R2/C3 form the low pass? Probably just my confusion with definitions. Either way, I require a bandpass filter with the low cut-off defined by R3/C1 and the high cut-off defined by R2/C3. Everything between these points should be passed with as flat a response as possible.

    I should add that the core to shield capacitance of my 2-metre cable is specified as "<90pF/m" so that will have some effect on the high cut-off. Cable capacitance is swamped by the capacitance of the piezoelectric disk though.

  • Hi,

    the capacitance of piezo and the cable capacitance form a capacitive voltage divider.

    Can you show scope plots (DC not AC) from the input and output of U1?

    You should keep in mind that U1 is a micropower OPAmp with very limited bandwidth. These OPAmps can behave very strange with too fast input signals. Maybe you should use a faster OPAmp at this place for the first experimenting.

    Kai
  • Thank again, Kai.

    By DC scope plots, do you mean disconnect the piezoelectric disk/cable and inject, say, 1V d.c. between the input to R2 and GND? Presumably, the output will saturate as the d.c. gain is very high? I don't quite understand your requirement but will happily carry out the test if you could clarify.

    "the capacitance of piezo and the cable capacitance form a capacitive voltage divider." Please can you explain this in reference to your diagram below? I thought the cable capacitance and piezo capacitance were in parallel. The voltage across Cp and Cc below is 0V.

    I went for LMC6041 because, in its data sheet, its applications include "Charge Amplifier for Piezoelectric Transducers". But I agree, it does have a GBW of only 75kHz. Please could you recommend an alternative with rail to rail output. It doesn't have to be low power.

  • "Please could you recommend an alternative with rail to rail output?" TLE2071CPE4 only swings +/- 3.4V but might be a possibility.
  • Hi D B17,

    Thanks for the information and scope shots.

    Please see attached couple alternative parts that you may find useful for the input stage.

    Additionally, please refer to the attached link for stability simulation and analysis. it discusses compensation techniques for improving phase margin and stability. https://training.ti.com/ti-precision-labs-op-amps-stability-6

    Regards, 

    -Mamadou

  • Thanks Mamadou.

    Unfortunately from your list, only the LMC6041 (which is the one in my circuit) and OPA130 will operate from +/-5V. As I said in my original post, I do need a wide dynamic range as close to +/-5V as possible. OPA130 is faster than LMC6041. Unfortunately, I can only get it in a surface mount package. I could solder it to a break-out board possibly.
  • Hi,

    you wrote: "By DC scope plots, do you mean disconnect the piezoelectric disk/cable and inject, say, 1V d.c. between the input to R2 and GND? Presumably, the output will saturate as the d.c. gain is very high? I don't quite understand your requirement but will happily carry out the test if you could clarify."

    The two scope plots above were carried out with the scope input in "AC" mode. I would like to see scope plots with the scope input in "DC" mode.

    You wrote: " "the capacitance of piezo and the cable capacitance form a capacitive voltage divider." Please can you explain this in reference to your diagram below? I thought the cable capacitance and piezo capacitance were in parallel."

    This is no contradiction:

    Kai

  • Thanks for your explanation of the voltage divider, Kai.

    "I would like to see scope plots with the scope input in "DC" mode."

    I applied a mechanical sinusoidal vibration of 22Hz to the piezo disk. Here below is the DC oscilloscope trace of U3's pin 6 output (which is connected to Ch2 on the scope). The "0V" axis exactly bisects the top half of the screen from the bottom, so the output shown on the scope has a d.c. offset about +0.8V. This is adequate for my ADC.

    I then distorted the mechanical vibration momentarily (by greatly increasing the amplitude and frequency). After that, I returned the vibration to 22Hz and the output then appeared as shown below:

    Finally, I switched off all vibration to the piezo disk. The output from U3 was as shown below:

    Finally, here below is the breadboard layout. The BNC connector in the bottom left is where the coaxial cable is joined to the circuit. The three amplifiers U1, U2, U3 are laid out left to right.

  • For some reason, some of the images in my previous post didn't upload. I'll re-post below:

    I then distorted the mechanical vibration momentarily (by greatly increasing the amplitude and frequency). After that, I returned the vibration to 22Hz and the output then appeared as shown below:

    Finally, I switched off all vibration to the piezo disk. The output from U3 was as shown below:

    Here below is the breadboard layout. The BNC connector in the bottom left is where the coaxial cable is joined to the circuit. The three amplifiers U1, U2, U3 are laid out left to right.


  • Hi,

    now I can see the photos  :-)

    Kai

  • Thanks, Kai !

    ".... so the output shown on the scope has a d.c. offset about +0.8V ..." I meant 1.8V
  • Hi,

    take care, when beating a piezo forcefully it can generate hugh signal pulses. 100V and more can appear at output terminals of such a piezo. It's no good idea to give such a high pulse to the input of a CMOS OPAmp. Phase reversal, latch-up or even destruction can occur. I would limit the signal voltage of piezo by the help of two antiparallel clamping diodes.

    Kai

  • Hi D B17,

    Are you still observing the same issue as you previously described?

    Thanks for updating us.

    Regards,

    -Mamadou
  • Hi Mamadou

    I haven't sorted the problem yet. I wonder if the parameters of U3 are causing the problem? When I move my hand near the scope probe on U3 pin 6, the amplitude of the oscillation diminishes. The scope is the only load on the output on pin 6. Could it be that the capacitance of the scope and probe is causing a problem for U3?

    I tried putting a 100 ohm isolation resistor in series with pin 6 and monitoring the oscilloscope signal on the other side of that resistor. This didn't seem to help much.

    On August 5, you wrote: "I simulated the 3rd stage of your circuit as shown below and i can observe a very low phase margin at 17.7 which in combination with your first two stages may be the cause of the oscillation. Additionally, notice also the small bandwidth of the 3rd stage which could cause oscillations if your signal at stage 2 is out of bounds."

    When you say the signal at stage 2 is out of bounds, what did you mean, please? The op amps are rail-to rail i/o.

    Also, you mention that the bandwidth of the 3rd stage is small. The GBW is 3MHz for that op amp, isn't it? My bandwidth of interest in 1 to 60Hz, which is tiny compared with 3MHz. What am I missing here?

    Thanks!

  • Hi D B17,

    you experience a typical breadboard effect, if the performance varies when you move your hand over the circuit. A breadboard is a rather improper method of wiring circuits, because the wires of components are much much longer than when the components are directly soldered into a PCB. By this every component reacts with any other via stray capacitance coupling and its difficult to get proper results. Then there is this big stray capacitance between the connector stripes of breadboard. And finally all these contacts are located close to the underlying metal plate which also increases the stray capacitance and acts as an antenna for all sorts of interference. One remedy is to connect this metal plate to the GND terminal of breadboard. Sometimes this helps...

    Cut the wires of components so that the components sit close to the breadboard. Avoid that components from neighboured OPAmps come each other too close. Avoid long running wires. Harden the signal ground wiring by adding redundant wires forming a mesh. All this can help to make the breadboard looking less like a breadboard and more like a proper PCB.

    Then, limit the signal of piezo by antiparallel clamping diodes. This is especially important when working with CMOS-OPAmps which so often suffer from latch-up effects.

    And finally, shield the circuit by a metal enclosure which you connect to signal ground. Even only shielding parts of the circuit against each other can tremendeously help.

    Divide and conquer: Go forward step by step. Start with the first OPAmp stage and make it work properly before you add another OPAmp stage. Only if the first stage works without any problem, add the second stage. Again make the both OPAmps stages work properly before you add the third OPAmp stage.

    Kai
  • Thanks, Kai, I will try this. Thank you for taking the time to write a proposed solution in so much detail.

    I used a second oscilloscope probe to monitor the output of U1 when the output of U3 was oscillating, I found that when I touched the second oscilloscope probe to U1, the oscillation at U3 stopped!

    I'm going to rebuild the circuit on a different breadboard using the your guidelines. Thank you for your support.
  • Hi D B17,

    when I have to develop a circuit I usually route a PCB with the test circuit. So, I do seldom breadboarding today. But when I was young and PCB in small quantities were far too expensive for me, I did always breadboard my circuits. From this time I can give you another hint: Your breadboard is clued onto a metal plate right? I learned that it is an advantage to move the breadboard a bit away from the metal plate and to connect the metal plate to signal ground at the supply terminal. By this the metal plate no longer acts as an antenna but now works as a shield. I think 5...10mm distance between the breadboard and the metal plate should be enough. You could insert a thin wooden board or something similar made from an isolating material.

    If the breadboard is glued too firmly and cannot be moved away from the metal plate you could buy a breadboard without a metal plate and mount it onto a metal plate as explained above. The metal plate works like a grounded metal enclosure then, as a perfect shield.

    Kai
  • Hi D B17,

    Thanks for updating us!
    My apologies for the the lack of clarity. The 3rd stage having such a small phase margin at 17.7 degree, any additional circuit or loads added could only degrade the phase margin of the overall system. One way to fix this issue, is reducing your unity GBW which will increase the phase margin in the 3rd stage.
    You're right in the assessment of your system BW and I meant by stage 2 signal being "out of bounds" (poor choice of word!) the frequency of your second stage signal being outside of your frequency of interest.
    In addition to Kai's detailed recommendations, build each stage steps by steps and do some sanity checks to ensure each stage is working as you expect (gain, Vin, Vout, Vcc, keep connections shorts, consider adding decoupling caps for your supplies as well) before moving forward to next stage and update us as you continue rebuilding the system.

    Thanks.

    Regards,

    -Mamadou
  • Hello Kai

    Some progress...

    I removed the components from my breadboard and used them to rebuild a circuit on a new breadboard, according to your guidelines. A photo is below (op amps left to right: U1, U2, U3; blue wires are ground grid). I kept the same op amps for the same positions.

    Unfortunately, the U3 output oscillation was still present, intermittently.

    HOWEVER... I found that I could trigger the oscillation every time by pressing my finger on the top surface of U3 (TLV2370). Only the black surface, I was not touching the pins or other components.

    I did try changing my oscilloscope probe, in case a damaged probe was the source of the problem, but the oscillations occurred whichever probe I used. It could be the oscilloscope itself, I suppose; that is probably the source of the 50Hz as there is quite a bit of mains 50Hz pick up on the probe leads, even when they are disconnected from the circuit.

    I have removed TLV3270 (CMOS) from position U3 and replaced it with a TL081 (FET). After 2 hours testing, the oscillations have not reappeared after the change of op amp, but I am going to let it run for a little while to see if they appear again. Will keep you posted.

  • Hi. My instability problem has not returned.

    The solution was:
    (i) Rebuild the circuit on breadboard with gridded ground and components with short leg lengths
    (ii) Change from CMOS to FET (U1, U2) and bipolar (U3) op amps

    Thank you Kai and Mamadou.
  • Congrats! :-)

    Kai