High Side Current Sense-Clarifications Required

Hello Hari,

Thanks for reaching out on the forum. So you can get the gain by setting the inputs to the LTC2063 amplifier to Vx. Thereupon, the upper node where Isense crosses Rsense has the voltage Vsense+Vx.   If you divide the difference between this node and the (-) input you get the IL current that passes through M1. The M1 transistor is operated in the saturation region so that it will drop whatever voltage necessary to maintain the drain current IL (I would look up regulated current sources if you need additional information on this). This current that passes through then creates the voltage across the RL resistor.  

REF is used to keep the LTC2063 operating within device specifications, as the supply can only be 5.5V above the negative supply or ground. M2 provides the LTC2063 negative supply a means to float with the common mode voltage which can be anywhere between 4.5V and 90V. D1 helps with biasing M2.

We actually have a similar circuit here and we show how to design for floating the device ground. Another thing to note, if you do not need such a common mode voltage, you might consider our INA190 (VCM<40V) and reduce your BOM count. Otherwise, possible TI substitutes for the LTC2063 include the LPV811, LPV821, and OPA369.

Hello Hari,

To determine if your Vgs is within the saturation region, it may help to first derive the curve that separates the saturation region from the triode region. You can do this through two different methods.  The first is to calculate the overdrive voltage for a given drain current value.  The overdrive voltage (Vov) corresponds to point on the above said curve. The formula for Vov can be seen below. 

Kp is known as the transconductance parameter and may or may not be found in the datasheet.  However, regardless of whether it is in the datasheet, it should be in the simulation model.  If it is not in the model, then it can be calculated from Uo and Cox, which should be in the model.  BSP322P has kp defined in the model.  However, it appears that Infineon defined it differently for certain conditions.  If you know which sub-model corresponds to your system conditions, you can pick the correct kp.  Otherwise, you may want to proceed with the alternative method.

For method two, you can do some approximation to determine roughly what Vov would be.  We know that the general equation for a parabola is (x-h)^2=4p(y-k), where (h,k) corresponds to the vertex, which in this case is approximately at (0,0).  If we use the ID vs VDS curve in the datasheet we can approximate p, which for me was around 1.4.

Once you have calculated a V_ov for a given I_D, I would then use the typical V_TH value in the datasheet to get V_GS.  You can verify through measurement if your VGS is around this value and confirm that the device is in saturation.  You could also take measurements while raising and lowering the common mode voltage to your amplifier to see that the current stays stable while V_DS changes.

The reason there is a 100k resistor is that the amplifier only has so much drive capability and the input capacitance of the BSP322P may make the amplifier unstable.

For stability, the following must be satisfied: 

Hello Hari,

I am not sure where you get 1uA for the REF. Based on the datasheet, it appears that REF can provide the proper voltage drop for reverse currents above 500nA up to 10mA (see figure below).

For M2, the diode can have a forward voltage lower than 1V according to the figure below. Due to the quiescent current of the LTC2063, C4 will charge up to a voltage that is above ground such that |V_GS|≥|V_T| and most likely such that |V_DS|>|V_GS|-|V_T|. The diode keeps the quiescent current from flowing across the 499K and also ensures that that VGS does exceed the gate source voltage specification in the datasheet.

As for the resistor, I have been told that a general rule of thumb adding a resistor and lowering the pole frequency typically helps. However, upon looking at the open phase gain plot in LTC2063, it does look as though you could run into some issues if the pole is too low as you may have the phase reach -180 degrees before the gain reaches 0dB. In that case you would have a negative phase margin, and a negative gain margin. Keep in mind it takes about 3 decades for the phase to drop 90 degrees for a single pole, while the gain will only drop 20dB per decade. For a little more information on this, I would recommend the following link. Otherwise, I would refer to one of the analog books by Razavi, Sedra and Smith, or Gray and Hurst.

Caps C3 and C2 I believe are outside of the loop and are meant for filtering the output. These can be calculated according to you R_DS range and the minimum bandwidth you need to measure in your system.

Hello,

Tha 1 uA appears to account for device variation as some devices may have a minimum operating current as high as 1uA.  I presume any devices exceeding that specification are discarded and not shipped.  Otherwise the typical devices most likely have performance similar to the graph in my post above.

For fast  changes in the common mode voltage  and the lower node of REF, the cathode will be a forward voltage drop across the 1N4148 as the 10uF will prevent the voltage from quickly changing on the cathode side of the IN4148.  Once the voltage across R3 is static. The cathode side voltage will continue to increase as the cap charges from the LTC2063 supply current.  Once the cap charges sufficiently high (|VS|=|VTH|), the MOSFET turns on.  The circuit I have below illustrates this.  In this case I used a 2N6804 which has a threshold voltage of about -3.7V.  

The quiescent current (supply current) comes from the positive supply side and runs through the part.