INA282-Q1: response time

Hi Koji,

Yes that’s correct –“input drive” means a large differential input voltage.

Response time (or delay time) often refers to the time deference from the start of the input step to the start of the output step. Response time is not defined in the datasheet. The settling time refers to the time deference from the start of the input step to the moment when the output has entered and remains in a specified error band of the desired value. Therefore settling time includes response, rise and small signal setting time. I do expect “response time” is only a small percentage of the overall settling time in this case.

The closest data for settling time estimate is figure 29, which is a 4V step and the device remains in linear operation mode. The rise time is about 25uS. Since a -50mV to 50mV input range produces a 2V step, the rise time cuts by half. This, plus small signal settling and delay will be the total settling time. The delay contribution should be negligible relatively.

Regard, Guang

Hi Guang,

Thank you for your prompt reply.
I understood. And I have some additional question about Fig 31.

As can be seen from the figure 31, the delay time at rise and fall are different.
For example,the delay time at rise (from the start point of rise of input to the start point of rise of output.) is about 5us.
On the other hand,the delay time at fall (from the start point of fall of input to the start point of fall of output) is about 25us.

Why is the delay time different from at rise and fall?
Also Is there any variation of tha delay time? How much is the variation of the delay time?

Best Regards,
Koji hamamoto

Hi Koji,

Great observation– here is the reason why: the over drive is no symmetrical from the INA’s perspective. Since the INA output is biased at mid-supply, ie 2.5V,the INA never leaves linear range when swings low; while it is saturated when swing high. As a result, there is NO recovery time when coming back from the low to the high side; while there IS a recovery time coming from high to low.

If the “input drive” is symmetrical WRT the quiescent state, such as -1V to 1V, then we’ll see the low side delay time (technically it should be called recovery time) much longer than it is now.

Now back to delay time referenced in your original question – I’m sure there is variation in delay time (again not to be confused with recovery time we discussed above), however there is no data to quantify it. The overall settling time should be dominated by rise time.

Regard, Guang

Hi Guang,

I am sorry for the delay in my response. Now we are waiting the response from the customer.
If I got the response, I will let you know.

Best Regards,
Koji Hamamoto

Hi Guang,

I am sorry for the delay in my response.
We have two question.

As you mentioned , the delay time (means response time) might be shorter than the rise time.
However out customer is concerned the variation of that time. Because they have the over current problem. (the some IC has been broken due to the over current.) That is why they ask the variation of the time. As you said, I understand there is no data.
Can you provide us any reference value we can estimate. (We can refer the Fig 31. So ,it will be OK the percentage of the value at Fig 31 as well.)

>If the “input drive” is symmetrical WRT the quiescent state, such as -1V to 1V, then we’ll see the low side delay time (technically it should be called recovery time) much longer than it is now.

What is "WRT" ? And I do not understand why the delay time will be longer than now if the input range is -1V to 1V.

Best Regards,
Koji Hamamoto

Hi Koji,

Sorry for the delay, somehow I missed your message until today.

Since we don’t have a spec for the delay time, I’ll go out on a limb and guesstimate, to the best of my knowledge. The rise time can be estimated based on typical slew rate of 0.2V/uS.

If the output is not saturated, the delay can be ignored; otherwise the typical delay is about 20uS based on Figure 31. A caution though this is not a fixed number generally speaking, the harder the output is driven to into saturation, the longer it takes to recover.

If we ignore small signal settling time which can vary greatly depending on accuracy requirement, then we can estimate the total settling time to be 5/0.2=25uS if the output swings 5V and is not saturated; 25uS+20uS=45uS otherwise. SR is directly related to the quiescent current of the device, which is normally tightly specified and controlled. Therefore I would venture to guess that the slew rate may vary 10% if you must have a number. Slew rate also tends to decrease as temperature decreases.

Figure 31 input drive is not symmetrical from the INA’s perspective in that the output swing from midsupply to 5V. This is the reason why there is a delay on the falling edge, but none or a negligible one on the rising edge. WRT stands for “with respect to”, I meant to say that the input drive is not symmetrical with respect to the quiescent state of the output in Figure 31.

Regard, Guang

Hi

Thank you for your reply.

This is very difficult to understand for me. So that, I summarized your answer as below. Please correct me if my understand is wrong.And I have some question.(Q1~Q3)

At Fig 31, the condition is V+=5V and V+IN=12V ,VREF1/2=2.048V , input drive=1V to 0V.
1. As you mentioned, at the input from 1V to 0V the delay time is calculated as below
delay:20us + SlewRate:14.7us @0.2V/us (output range = 5V~2.048V =2.95V)
2. At input from 0V to 1V, the rise time (SlewRate) is dominant in this area.
delay: a few "usec" + Slew Rate:14.7us

On the other hand, if the input drive is 0V to -1V, the saturation area is opposite of above. (the saturation area is 5V rail and GND rail.)

3. At the input from 0V to -1V,
delay:a few usec + Slew Rate:10.2us @0.2V/us ( output range = 2.048V~0V)
4. At the input from -1V to 0V,
delay : 20us + Slew Rate :10.2us

Q1: Is my understanding correct?

Q2: If this is correct, how much is the variation of the delay time and slew rate that we can estimate? As you mentioned at previous post, the slew rate is around +/-10%.
How about the delay time?

Q3: And I have a question about Fig 31. Is this the over driving condition?
At Fig31, the input voltage is 1V to 0V. And the output range is 5V~0V (mid supply=2.048V)
Because the gain is more than 50V/V that this device has.

Best Regards,

Koji Hamamoto

Hi Koji,

Q1- Yes, the understanding is correct.

Q2- again I don’t know the exact variation, 10% is just a guess. You could as well use 20%. I wish I have a better answer but simply don’t. If the input overdrive remains the same, I would use the same % in calculation. However if the input overdrive is different, then the delay time will likely be different as well. For example, if we have two input levels 1V versus 100mV, the delay time for these two situations will be different. How different? I don’t know. In general the higher the overdrive is, the longer the delay time.

Q2- yes this is an overdrive condition on the high side. Since the output is clipped by the 5V supply. If the input low is -1V instead of 0V then it is overdriven in both directions and we should see a big delay time on the low side as well.

Regard, Guang