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PGA112: Common Mode Input Voltage

Part Number: PGA112


I have a question regarding -> Datasheet  9.1.1 OPAMP: Input Stage, transition between the NMOS and PMOS transistor.

Typically the offset voltage starts to show big deviations around VCC-1.5V (Fig. 66 and 67). This is different on each device, and probably also temperature dependent. On the DS the Input Offset Voltage for VCM is specified as 2.5 and 4.5.

if the PGA112 is supplied with 5V, what would the max allowed Common Mode Input Voltage be, where the Offset Voltage still doesn't show big deviations?



  • Hi Gerardo,

    I would keep the common mode input voltage under 3V.

    By the way, I wouldn't call a change in offset voltage from 25µV to 75µV (typically) a "big deviation". :-)

  • Hi Gerardo,
    Based on the offset voltage specification in the datasheet, the maximum spec of ±100uV offset is given at 2.5V Vcm. I'd suggest 2.5V as a conservative limit, though Kai's suggested 3V common mode voltage may also be reasonable. Ultimately, all that we can say is that the crossover region appears 1.5V from the positive rail.