Hi,
I have a question regarding -> Datasheet 9.1.1 OPAMP: Input Stage, transition between the NMOS and PMOS transistor.
Typically the offset voltage starts to show big deviations around VCC-1.5V (Fig. 66 and 67). This is different on each device, and probably also temperature dependent. On the DS the Input Offset Voltage for VCM is specified as 2.5 and 4.5.
if the PGA112 is supplied with 5V, what would the max allowed Common Mode Input Voltage be, where the Offset Voltage still doesn't show big deviations?
Thanks!
Tadeo