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INA2181-Q1: , INA4181-Q1 --- Thermal Stability of the Gain value

Part Number: INA2181-Q1

What would be the expected thermal stability/drift of the Gain value when external resistors are added at the inputs of these amplifiers for filtering? (For example, two 10-Ohm resistors, per datasheet example at 9.1.3 Signal Filtering).

It is understood that in this configuration the Gain will have an additional initial error of about -0.83 %, this is not critical in our application, as it will be calibrated out.

However, we are interested in the magnitude of the thermal drift for the Gain in the above configuration; there are no indications in the datasheet for that parameter. 

Clearly, the excellent datasheet value for the "Gain error vs temperature" (1.5 ppm/°C typical, 20 ppm/°C maximum) can not be maintained.

From various AppNotes and Reports, it seems that the internal resistors are optimized for incredibly tight thermal tracking, but the absolute value of the on-board resistors can vary as much as +/- 30 % or more.

Furthermore, the influence on the Gain is manly from the Bias network at the Inputs (with equivalent resistance of 1250 Ohms ?) What would be the TCR value of that Bias network?

  • Hi Victor,

    The INAx181 family is designed with zero drift technology, that’s why the exceptionally low drift is achieved. The internal 1250 resistor drift is typically in the low single digit ppm per degree C. Therefore it can be thought of as flat over temperature for practical purposes. As a result, you might be able to estimate the system error drift based solely on the external resistors.

    The internal resistor absolute value can vary up to 20%. Please take this into account if necessary.

    Please let us know if you have further questions.

    Regards, Guang

  • Hello Guang,

    Thank you for a quick response.

    Unfortunately, what you say sounds too good to be true... :-)

    Integrating resistors with single-ppm per °C thermal drift is not possible on the chips. If this was true, all precision resistor manufacturers (Vishay, Ohmite, Riedon, Susumu, Panasonic, Yageo -- I'm sure I missed a few) would quickly be out of business. Even for them, making a single-ppm per °C resistors is a big problem, typically involving exotic metals and oxides with special processing, which is not possible on ICs. And they are LARGE in size...

    The resistors that are integrated into ICs are more in line with +1700 ppm to - 650 ppm per °C thermal drift.

    Now, it may be possible, that the differential input resistance for INAx181 devices is not a physical resistance at all, but an equivalent resistance created by some kind of a switched-capacitor circuit. This must be true for the INAx181 amplifiers, because it looks like at least some (significant) portion of the supply current is drawn from the Common-mode voltage present on the inputs, once it crosses the supply voltage of the IC. This is clear from the charts for the "Input Bias Current vs Common-Mode Voltage" and "Iq vs Common-Mode Voltage". There must be a charge-pump arrangement supplying the operating current for parts of the IC, and that charge-pump is quite efficient, it is not a built-in LDO that would waste most of the energy when powering a 5 V circuit from 26 V.

    In this case the thermal drift will depend on the drift of the values for the integrated capacitors (which are also not very stable, but perhaps have much better TC than integrated resistors), and on the frequency of the built-in clock. The clock itself will depend on at least one capacitor and one resistor, or perhaps, gate delays in some ring-oscillator scheme.

    Careful IC design may try to compensate the drift of the capacitors with changes in the clock frequency, but doing it to the tune of single-ppm is not really feasible.

    So -- that's why I say that the single-ppm drift of the equivalent differential resistance at the inputs of the IC sounds to be too good... :-)

    Zero drift technology that you mention surely applies only to the stability and drift of the input offset voltage, and perhaps to the stability and drift of the gain value - without extra resistors at the inputs.

    Please, if at all possible, reach out to the original design and characterization team, and ask them about the issue I am pursuing:

    Just to be clear, we are interested in the effect that differential input resistance will have on the thermal stability of the Gain, for the case when extra resistors are connected in-series with the inputs.This happens, essentially, because the equivalent differential input resistance forms a simple voltage divider together with the extra resistors added at the inputs, and thermal stability of the equivalent differential input resistance will thus have a large effect on the thermal drift of the overall Gain value.

    Please ask:

    1.) Is there any characterization data (that can be shared with us) that would support ANY stated drift levels.

    2.) We are not actually concerned with the absolute value of the drift, but only with the variation of that value in a large production lot for the ICs.

    Just in case it matters, we are planning to use the "A1" variant of the IC (with 20 V/V Gain), current sensing will be done at the Common-mode voltage that is close to the GND pin of the IC (e.g. low-side sensing), the IC will be powered with 5 V.

    Our application is large-volume automotive; the INAx181-Q devices are a great fit, almost perfect except for the question I am asking. For us to be able to use the device, we have to have a proof that it will work in the application, trial-and-error or characterization in our lab is not an option.

    Can you also please answer the following (perhaps) related question: In the Figure 21 ( on page 11) of the SLYS018A –APRIL 2018–REVISED JULY 2018 datasheet for the INAx181-Q part, the Input Bias Current vs Common-Mode Voltage is shown for the condition of Shutdown. Could you explain how is it possible that the IC is generating some (admittedly small, about -6 µA) current when its supply voltage is ZERO, and the Common-mode voltage is also ZERO? What energy/supply connection does this current come from? Does the INA device have an embedded source of energy? :-)

    The chart in question is attached (if it does not come through, please look it up as stated above:Page 11 Fig 21 of INAx181-Q datasheet).

    Thank you for your help!

    Fig 21 re question to TI for INAx181_Q1.pdf

  • Hi Victor,

    There are certainly resistors with TC in the thousands of PPM as you mentioned. That is exactly why I said, for practical purposes you might only need to care about the TC of those external resistors. The INAx181 internal resistor is indeed that good. If you must have some numbers associated with it, the range is ±25ppm/⁰C. The mean is -3ppm/⁰C, that’s why I said earlier it is flat. I think this answers your question 2). However, to your question 1), there is no characterization data as this is guaranteed by fab PDK.

    To be fair to resistor vendors, they do offer a wide selection of resistors with exceptional low TC, here is a link to Digikey. Obviously we’re not the only one who knows how to make good resistors.

    Regarding your question concerning the -6uA current – there are sensing circuits (the 1250 resistors are part of it) inside the chip. Path exists between the inputs and VDD. This is why the input bias current graph looks the way it does. The negative sign simply means the current flows out of the device, rather than flowing in.

    Regards, Guang

  • Hello Guang,

    Thank you for your response!

    Unfortunately, your explanation re: bias current at 0 Common-mode in shut-down -- is not really plausible. Even if connections exist between the inputs and Vdd, it is specifically stated that Vdd is ZERO for this chart, so no leakage can come this way.

    However, I believe we figured it out.. On the top of that Page 11 (where the Chart is located) there are testing conditions that apply unless specifically stated otherwise.

    While the condition of the power supply (Vs = 5 V) is superseded by the Power-down state of Vs = 0, the condition of Vref = Vs/2 still probably applies in the sense that Vref = 2.5 V.

    A potential of 2.5 V with the resistance of about 500 k (one resistor from Vref pin to Amp+ and then smaller resistor from Amp+ to Input+ pin, as shown in the Power-down section of the datasheet) will produce leakage of -5 µA.

    When I zoomed in to the chart and measured the relevant points with a ruler, an estimated value of leakage at 0 V Common-mode voltage came out to about -5.14 µA  -- close enough...

    This also explains why the bias is zero when the Common-mode voltage (also measured/estimated with a ruler on the chart in Figure 21) is some 1.48 V. This is a voltage that is imposed on the inputs with the divider that is made-up from internal resistors from the Vref and Vout. It is not exactly 1/2 of Vref because the connection from the output pin to GND (as stated in the Power-down section of the datasheet -- low impedance) is not so low at about 250 k; more likely that the output is simply biased one diode drop of about 0.46 V above GND for the Power-down condition. The current from Vref at this point will be close to only 2 µA.

    This also explains why the bias is ZERO in the chart of Figure 20 (powered-up condition), at the Common-mode voltage of 1.21 V. When powered-up, the unit will actively drive the output to 0 V, so there will no longer be a diode drop, and the divider from Vref to Vout will divide the reference voltage exactly in half (well, 1.21 V is close enough match to the expected 1.25 V, and probably there are some other minute leakage paths from the inputs to GND that reduce this voltage).

    Mystery solved...

    Thank you for your DigiKey link -- I was completely unaware that DigiKey, Mouser, etc. sell high-precision resistors.... :-)

    I have just one remaining question: What is the configuration at the input that draws the additional bias current when the inputs are biased above the Vs? Please see the attached sketch -- I see only three (3) possibilities here, please let me know which one is actually employed -- are there actual physical resistors at the Input, or it is an apparent equivalent resistance due to switch-cap pump action?

    If there are actual resistors, I will assume, as you stated in you previous message, that the TCR of these resistors is ±25 ppm/⁰C Maximum and -3 ppm/⁰C typical.

    Thank you!Q to TI re_INAx181_Q1 input bias configuration.pdf

  • Hi Victor,

    As always, glad to help in any way we could.

    Regarding you question “What is the configuration at the input that draws the additional bias current when the inputs are biased above the Vs?” – Configuration A is the closest representation of the real circuit, only each resistor is 1250. It is quite impressive that you are able to figure out a lot of the inner workings of the IC.

    And yes, these two are the resistors we talked above regarding the flat TC.

    Regards, Guang

  • Thank you Guang, I consider this thread resolved!