Hello e2e,
Follow-on questions from https://e2e.ti.com/support/data-converters/f/73/p/772076/2857052
1) Please consider this circuit:
_______ ___________
Signal----| |--40Ω--| |
|LMH3401| |ADC12DJ3200|
VDC--50Ω--|_______|--40Ω--|___________|
|
v
In my design I want the average voltage presented to the LMH3401 inputs to be different. That's because V_IN+ is not symmetric, i.e. the voltage duty cycle is far from 50%. In other words, the DC voltage of V_IN+ - V_IN- is far from 0. Does it cause problems in the amp to not have a balanced input like that?
2) Please consider this circuit:
_______ ___________
Signal----| |---| |
|LMH3401| |ADC12DJ3200|
VDC--50Ω--|_______|---|___________|
|
v
If one connects the LMH3401 V_OUT+- directly to ADC12DJ3200 INA+- without 40 Ohm resistors on a board (trace length < lambda / 10) thus bypassing the 40 Ohm resistive loss, would the 0.55 voltage loss from the 40 Ohm resistors be improved to ~1 in practice? Would this circuit work in practice for broadband inputs? What would be the deviations from specified performance?