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LMH6522: SPI Timing Requirement

Part Number: LMH6522
Other Parts Discussed in Thread: LMH6521

Hello, 

I have a question about LMH6522.

[Q1]


(D/S, p5)

1. Is the maximum value of fSCLK unspecified?

2. Is the minimum value of fSCLK really 20 MHz?

[Q3]

Please tell me the SPI Timing Requirement.


(D/S, p23)

Best Regards,

Kaede Kudo

  • Hey Kaede,

    Some of this information can be found in the datasheet for the LMH6521 datasheet which is from the same family of devices. Since the timing requirements seem to be missing from the datasheet of the LMH6522, I would recommend using the timings in the LMH6521 datasheet. We will look into fixing this for future reference.

    Best,
    Hasan Babiker
  • Hello Hasan,

    Thank you for your reply.

    I referred to the LMH6521 D/S.

    I understood it like the comment of the blue letter below, but is it?
    Thank you for your review.

    [Q1]


    (D/S, p5)

    1. Is the maximum value of fSCLK unspecified?
    -> fSCLK(Max serial clock frequency) is 50MHz(typ).

    2. Is the minimum value of fSCLK really 20 MHz?
    -> It is not 20 MHz.
     Not specified
     There is no problem if it is driven at 10 MHz or less.

    [Q3]

    Please tell me the SPI Timing Requirement.


    (D/S, p23)
    -> LMH6521 D/S.

    Best Regards,

    Kaede Kudo

  • Hello Kaede,

    Yes the blue text summarizes my response. In the case of the 2, the SPI min requirement is set to 20MHz since this is the lowest frequency tested by the ATE. Because of this, going lower than 20MHz cannot be guaranteed to provide the same functionality, however it should still work.

    Best,
    Hasan Babiker
  • Hello Hasan,

    Thank you for your fast reply.
    I undesrstood your comment.

    Best Regards,
    Kaede Kudo