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TLV9052: Why the slew rate increases as the capacitive load increases?

Part Number: TLV9052
Other Parts Discussed in Thread: OPA192, OPA835

Hi, I want to ask that why the slew rate increases as the capacitive load increases?

  • I presume you are looking at that kind of odd front page plot.

    People confuse slew rate with rise time often. That plot might have been a small signal non-slew limited measurement with increasing cap load where increasing the cap load was reducing the phase margin creating an apparently faster rise time, converted to an increasing "slew rate" here erroneously - just a guess.

    There is a pretty thorough discussion of relating linear rise time to slew rate in these two articles - probably more than you want, but this explains it. This is surprisingly confusing and folks doing data sheets get this wrong all the time - which doesn't help. Just a quick summary for what is in here - a slew limited edge by definition is a fixed dV/dT - rise time won't give that to you and in fact underestimates the peak dV/dT on a 2nd order non-slew limited step by quite a bit.

  • Hi Rui,

    The graph Michael refers to is correctly labeled and is NOT small signal settling. The graph shows Slew Rate vs. Load Capacitance for a large step input voltage.

    The TLV9052 uses slew boost to increase the slew rate of the device. When the inputs of the op amp get pulled apart enough slew boost kicks in to increase the slew rate of the device. I believe that the slew rate is increase with load capacitance because the load capacitance causes the inputs to be pulled apart more for a longer period of time causing the slew rate to increase and be "on" longer. For an explanation on slew rate I recommend watching our TI Precision Lab videos on Slew Rate.

    Thank you,

    Tim Claycomb

  • So any idea what the step size and input edge rate for that plot, it is a bit unusual and I am not sure how you would use it - buried in that time waveform I would also expect the time waveforms to vary quite a lot increasing cap load

  • The step size is likely ~4Vpp (like what is shown in all our large signal settling graphs) and it is a fast edge rate (step input). The point of the graph is to bring awareness to a user that slew rate will increase with an increase in load capacitance. Eventually the graph will flatten off.
  • SLew rate changes with lots of things, not just cap load as implied here (although that is a new one for me)


    1. Slew rate is often much diff. inverting vs non-inverting - also rising and falling as shown in the OPA192 plot in that article where the faster rising edge of 20V/usec was used for a spec instead of the slower falling 17V/usec. This is one of the real traps in building like active filter design tools - you want the stage to stay linear so you check for slew rate margin where using 20V/usec spec on the OPA192 is misleading - normally I target a min 1.5X margin recognizing how slippery slew rate specs are.
    2. I could not find any mention of slew enhancement int he data sheet and (everything is relative) 15V/usec does not normally get into high slew rate categories (the lowest quiescent, slew boosted VFA is the OPA835 250uA quiescent with a true slew boosted input giving 160V/usec.
    3. I was going to run some phase margin sims vs cap load to see if I could drill down on this a bit - no model that I can find.

    Oh well, let it go -just kind of unique plot - I don't remember seeing it before anywhere but its a big world out there.
  • The TINA model can be found in the Tools and Software tab on the product webpage.

    Hi Rui,

    If you have any additional questions. Please let me know.

    Thank you,

    Tim Claycomb

  • Thanks, must have been looking at a different part by accident.

    Tried to do a little bit of sim work onthis, pretty strange results non-inverting gain of 1. The 50pF is about 2dB peaking and 8Mhz BW, the 350pF load is 10dB peaking and 4.5MHz F-3dB - so the small signal shapes are changing a lot across that front page x-axis - but then, maybe the test was done inverting? with what R values in that case - have to move along, this is not going anywhere - there are a lot of useful labeling that seems to be absent in the PDS plots.
  • Hi Rui,

    If there is anything else you need please let us know.

    Thank you,

    Tim Claycomb
  • Hi Tim, hi Michael,

    in my simulations the slew rate decreases from 15.7V/µs to 14.4V/µs when increasing the load capacitance from 0pF to 350pF:



  • Hi Kai,

    This is likely because this behavior is not modeled in the TLV9052 TINA model.

    Thank you,

    Tim Claycomb
  • Hi Tim,

    yes, that makes sense.

  • Hi Kai,

    Glad I could help.

    Thanks you,

    Tim Claycomb
  • Yes Kai, that is what I saw also where the low end of that plot looked slew limited in the step response but as you went higher in Cload that ringing indicates more of a linear underdamped response - odd, I think it would be safe to say there is a lot more changing with cap load than just the slew rate in that plot.
  • Hi Michael,

    The graph represents the correct performance of the device. That the slew rate increase with cap load. Yes, there will be more overshoot with a higher cap load, as it will be with any amplifier. 

    -Tim Claycomb