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AFE032: How big is the fifo?

Martin Drinnan72
Prodigy 10 points
Part Number: AFE032

I cannot find in the datasheet how big the fifo is for the afe032. Is this number available?

Additionally, the XCLK and SCLK lower frequency limits are listed differently in the datasheet (this is not relevant for our application, just an FYI).

XCLK lower limit is listed as 5MHz in Electrical Characteristics: Digital section, and 10MHz in AFE032 Clock Requirements.

SCLK lower limit is listed as 20MHz in SPI Timing Requirements, and 14MHz in AFE032 Clock Requirements.

  • 0
    TI__Prodigy 420 points

    Hi Martin,

    Thank you for pointing out the discrepancies in the datasheet. I will relay the information to the team responsible for the AFE032 datasheet.

    I have also reached out to the team responsible for the AFE032 design to get clarification on the ASYNCH FIFO depth and will provide an update if/when that information is available.

    In the meantime, here are their recommendations with respect to the DAC interpolation chain/clocking:

    The interpolation chain is tested and validated for a couple of boundary conditions and these are what the user must keep in mind when programming for a custom DAC up-conversion rate.

    • The process works for a max of 6MHz i.e., DAC cannot handle anything more than 6MHz.
    • The max data rate that the AFE can handle presented to it from an external processor is 1.2MSPS