Hi TI-team
Is the surge withstand voltage when applied under the surge conditions shown below protected ?
Pulse1 Ri=10Ω td=2ms 500pulse Vp=-100V
Pulse1b Ri=10Ω td=2ms 500pulse Vp=57V
Pulse2 Ri=2Ω td=50us 500pulse Vp=114V
Pulse3a Ri=50Ω td=0.1us Vp=-150V
Pulse3b Ri=50Ω td=0.1us Vp=114V
Hello Koji,
Typically if we can meet a special specification like ISO 7637-2,16750-2, we will say so in our datasheet. As this datasheet does not mention it, I do not think we will guarantee that your device will survive those conditions. Despite the datasheet not specifically stating whether it can meet your criteria, we may be able to extrapolate whether it can if you are willing to take the risk. For extrapolating the device performance, I think we could use the ESD ratings table specifications. Assuming I interpreted correctly the Jedec JS-001 test conditions utilized by the AEC Q100-002 standard, then the current profile looks like the plot below and the power time product can be calculated as below. As power relates to heat which is likely what would destroy the ESD diodes activated by a surge event, I think this might be a reasonable preliminary analysis approach. With a defined rise time, I think you can do a similar analysis of your power time products. If they come out lower, the device may be more likely to survive.
