Dear Support team,
Could you let me know the status of CMP1 OUT just after power on?
We found that CMP1 OUT is latched just after power on. Is it correct?
If it is ture, please let me know waiting time of RESET for avoiding latch of CMP1 OUT.
Best Regards,
Hirokazu Takahashi
Hello Hirokazu,
I ran some tests in the lab yesterday and I too observed CMP1 OUT latching high if reset is pulled to VCC when powering on. I also ran a test when Reset was pulled to gnd with the internal 2Meg resistor of the device and 10Meg of the Oscilloscope and probe. Those results can be seen below. From the second test the CMP1 out pin appears to rise briefly while the device is powered on. After the Vcc crosses a certain threshold, the device appears to enter the region of expected behavior and the device resets CMP1 Out to GND. The cutoff point for this region likely varies between devices due to manufacturing tolerance. The cutoff I would use to be safe would be the minimum Vcc of guaranteed linear operation (2.7V). Once the device VCC reaches 2.7V, you should be able set reset to high without triggering the comparator for a no load condition.
Figure 1: INA207 power-on, Reset pulled to VCC with 10k
Figure 2: INA207 power-on, RESET = OPEN
One method that I think might help is shown below. On the left, I show a voltage divider that represents a simplification of what I think may be on the RESET pin internally. The datasheet provides a detail that the pin is pulled low internally with a 2 Meg resistor. As such, the upper impedance should be at least 10x larger. Attached to the divider node (Reset Pin), I use a typical pull-up value of 10k (could be smaller too). This circuit will rise immediately with VCC. On the right, I have a potential workaround, which is a RC filter. The idea is that at turn on, the capacitor initially looks like a short to gnd and forces RESET to look relatively low for just long enough for the device to escape the region of operation that latches the comparator. Some adjustment of the resistor and capacitor values might be needed to make this work.
The other alternative would be to use a microcontroller to toggle the RESET pin once the device is properly powered.
Hey Hirokazu,
I went back and tested my proposed solution in the lab to determine whether it truly works and below is what I got with a 10kohm 1uF filter on the RESET pin like above. In the lab my supply slews up considerably slower than the simulation so the difference between reset node and supply potential is not quite so pronounced. However, it appears to create just enough delay for the internal detect circuit on the reset pin to have the device in transparent mode for the critical point that would otherwise latch the device. I would recommend to use a larger capacitor if you have a slew rate like mine or slower on the supply to ensure that for all boards you build this issue will not reappear.
