are their more performance data available from within the transistion-regions indicated in the data sheet section 8.3.2 Rail-to-Rail Input?
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The specification CMRR shows the performance difference between only operating in the NMOS and operating throughout then entire common mode range (both NMOS and PMOS input pair). Notice that the test conditions listed are for different common mode voltage ranges.
Also take a look at Figure 4 in the datasheet. This graph displays how the offset voltage changes over the entire common mode voltage range and displays where the transition region occurs.
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