Please see the attachment for my question.When test i short JP4 pin 1 and pin 2，and short JP5 pin1 and pin2，Remove R23 and R25.OPA2188 output test.pdf
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A phase shift between the applied input signal and the output of an integrator, passive or active, is normal. The amount of phase shift, which is equivalent to a time delay, is a function of the resistor and capacitor values in the Op amp feedback loop. If you want to reduce the 680 k feedback resistor to 100 k, then the 150 nF capacitor would have to be increased by a factor of 6.8x to obtain an equal time constant. There isn't anything else you can do to the OPA2188 integrator stage itself to maintain the same time delay if you want to decrease the feedback resistor value.
Keep in mind that if you do change the feedback resistor value to 100 k and want to maintain the same gain as with the 680 k, then the input resistor would need to be decreased by 6.8x.
An active integrator will integrate any of the input referred dc offsets components such as the natural voltage offset and offset due to input bias current. I expect that is the dc level that you are seeing at pin 7. The dc level will happen to be whatever it is at the moment you measure it. If the integration continues indefinitely, eventually the integrated dc will cause the Op amp output to reach one or the other supply rails. That is why most integrators include a reset circuit so that at some point the integration can start over and the dc can be set back close to zero. The reset circuit is usually a JFET or MOSFET transistor connected across the feedback components. The JFET or MOSFET when turned on appears as a low resistance across the integrator capacitor discharging it.
Precision Amplifiers Applications Engineering