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LM2902-N: high side voltage to current converter stability issue

Part Number: LM2902-N
Other Parts Discussed in Thread: TINA-TI, LM2902

I'm designing a voltage to high side current current source converter.

To check stability, I have broken the loop and measure the loop margin.
With R3=2k, C2=1n and R2=4k the phase margin is sufficient 53.56°.

But, When I look at transient results, I notice overshoots.
So, what's wrong?
Can you help me?

Kind regards.

  • Hi Sylvain,

    There may not be anything wrong with the circuit. Some overshoot (approximately 16%) is expected with 53 degrees of phase margin. How much overshoot are you measuring in simulation? It is difficult to tell from the images.

    As phase margin increases the overshoot will decrease. For example, if you increase the phase margin to 60 degrees you will only see ~8% overshoot. The important thing is that you do not see a sustained oscillation which indicates a clear stability issue.

    Thank you,

    Tim Claycomb

  •  Hi Tim,

    Tank you for your explanation.

    The positive overshoot is :(339.35µ-298.96µ)/298.96µ= 13.5%.
    and there is also an positive overshoot on AM1 when VG2 decrease. It's curious, no?

    Han can I increase phase margin?
    I did some tests with different values ​​for R1, R2 and C1; but in any case, I have not been able to increase the phase margin by more than 53.5 degrees.
    Remark: For my application, I need a bandwidth of  about 20 KHZ.

    Kind Regards.


    Sylvain

     V_to_I_2.TSC

  • Hi Sylvain,

    Is the op amp output railed to one of the supply voltages during the positive overshoot on falling edge condition?

    When I run the analysis myself and ensure the op amp output is not railed I do not see the positive overshoot you circled in your previous post. Please see the attached TINA file. I have also updated the TINA model to use our latest model version. It is always recommended to download the newest model version from ti.com when running a simulation.

    I believe increasing R5 is the easiest way to increase the phase margin of the op amp. But increasing R5 means that C1 and R2 may also need to be adjusted.

    V_to_I_2_TI.TSC

    Thank you,

    Tim Claycomb

  • Hi Tim,
    Thank you.
    No, the op amp output is not railed to one of the supply voltages during the positive overshoot on falling edge condition.
    With your simulation file, I see the positive obershoot during the falling edge when I increase the amplitude A of the unit Step voltage generator to 100mV .
    Then, I replaced T2 PMOSFET by a BC327-25 PNP transistor and R5 by 47k and there is no more overshoot.
    Have you an explanation?
    When I increase R5, and modify R2 and C1, the phase marging is increasing but only few degrees. Have you any suggestion to increase it more?

    Kind regards.

    Sylvain

  • Hi Sylvain,

    I'll need some time to look into why this is happening. I will get back to you by Wednesday of next week. It appears there is some sort of coupling occurring with the feedback capacitor, C1. When I decrease the capacitor C1 to 100pF the positive overshoot through meter Iload_high side goes away with a 100mV step input. I put some current meters in to see where the currents are flowing. Please see the attached TINA-TI file.

    Will your system actually see transient pulses like this when in production? 

    1512.V_to_I_2_TI.TSC

    Thank you,

    Tim Claycomb

  • Hi Sylvain,

    There may also be some coupling due to the capacitance of the FET between the output of the op amp and load resistor.

    Thanks,

    Tim Claycomb

  • Hi Tim,

    I think that our system will see transient pulses in production but with a rise time more important (about 500µs-1ms).

    If I reduce C1,  the phase margin will be too low.

    It's not a problem to use an PNP transistor instead of a mosfet.  I need to drive in worst case only 500µA.

    The more important for me is to have a stable system!!!.

    Thank you.

    Kind regards.

    Sylvain

  • Hi Sylvain,

    As long as the phase margin of the op amp is above 45 degrees the system should be stable. What I believe is happening is some current is coupling through the transistor. The positive overshoot on a falling edge does not indicate a stability issue. If the PNP transistor corrects the issue and works for your design I recommend using it. However, you must verify that the compensation components do not need to change with the PNP transistor in the circuit.

    Thank you,

    Tim Claycomb

  • Hi Tim,

    I realized two simulations:
    - simulation n°1: R2=2k, C1=1n, R5=100k, T1=BC327-25  
        - AC Analysis: phase margin=44.97°.
        - transient response: little overshoot.
        
    - simulation n°2: R2=200, C1=10n, R5=100k, T1=BC327-25  
        - AC Analysis: phase margin=50.19°.
        - transient response: big overshoot.
     
    It's curious that with a bigger phase margin, the overshoot increases.  Normally, it's the opposite.
    Did I make a mistake with open loop schematic and phase margin measurement?
    What do you think about it?

    Kind Regards.

    Sylvain

    simulation_n°1.pdfsimulation_n°2.pdfV_to_I_transient_and_bode.TSC

  • Hi Sylvain,

    What I believe you are missing in your simulation is Loop Gain. When measuring the phase margin of the circuit you want to look at the phase of loop gain not Aol. To measure the loop gain you will need to place a meter at the R2 C1 node. Placing a meter at the R2 C1 node will give you Aol*Beta, you can then back calculate 1/Beta (using the post processor in TINA) by dividing Aol/(Aol*Beta).

    Also, the larger positive overshoot on the falling edge does not necessarily indicate lower phase margin because I believe this is occurring due to coupling not instability. If it were a stability issue I would expect to see large positive overshoots and ringing for the rising edge and large negative overshoots and ringing for the falling edge.

    Thank you,

    Tim Claycomb

  • Hi Tim.

    I am lost....

    To do my simulation, I got inspired from another post from TI forum: https://e2e.ti.com/support/amplifiers/f/14/t/611850?LM2902-loop-gain-of-Voltage-controlled-current-source

    Cannot we use phase margin to measure stability of this system? Or must I use 1/BETA & AOL ?  
     -In my case, the output of my system is a current. Should not we use "output current" in AC analysis to check stability?
     -Where must be localised AC source to test loop gain. Should not we break the loop at the output?
     
    Could you help me  to check if my system is stable ?

    Best Regards.

    Sylvain

  • Hi Sylvain,

    Yes you do use phase margin to measure stability of this system. Everything in the forum post you provided is correct.

    The issue was with how you were measuring the phase margin. In your phase margin measurement circuit there was not a meter for AolB as indicated in the forum post you linked to. There was only a meter for Aol. To measure phase margin you must look at AolB. Please see below.

    To measure the stability using a small signal step input or closed loop AC analysis, you should always look directly on the output of the op amp even if the output of the circuit is a current. This is because the circuit output signal may have additional filtering that removes large oscillations occurring on the output of the amplifier. You would not want large oscillations on the output of the op amp for a robust design even if they get filtered out somewhere. Notice in the forum post you linked to the output of the amplifier is being measured for a transient step input to verify the output of the amplifier is not oscillating.

    The circuit you used in your previous post (shown above) to break the loop is correct, you just need to add a meter to look at AolB.

    Thank you,

    Tim Claycomb

  • Hi Tim,

    Thanks a lot for your explanations.
    It's now very clear!

    Best Regards.

    Sylvain

  • One curiosity I noticed.

    Sylvain is using the LM2902 model in the Tina library.

    Tim is using the LM2902 model which is on the LM2902 landing page.

    You can check this by using the "Enter Macro" function.

    The landing page model is the latest Green-Williams-Lis model, far

    better than the older National Semiconductor model in the Tina library.

    How much this has a bearing on the simulation I personally have not

    checked.

  • That's a good point! I highly recommend using the latest model on the LM2902 (or any device) product page. You can find the latest model version under the Design & Development tab.

    Thank you,

    Tim Claycomb

  • Hi Tim,

    Sorry, but I have other questions for you...
    I have modified my orginal design to change the slope of the V to I curve.
    Now, the positive input of the amplifier is a voltage reference and the input of the converter is at the top of R1. I(AM1)= f(VG1).

    I want to check to phase margin of  my new schematic.

     - I think I can break the loop as the same position (at the negative input of the amplifier) as the original design. Is it correct?
     - What become VG1? Should be it replaced by a constant voltage source?
     - How could I measure BetaAOL in this case?
     
     Thanks for your help.
     
     Best Regards.

    Sylvain




     

  • Hi Sylvain,

    Yes you will break the loop in the same position as the previous circuit and measure Aol*B at the same node. You should always represent input voltage signals as a short and input current signals as an open. The exception to this rule is for DC voltages that bias the op amp to put it in a linear region.

    Thank you,

    Tim Claycomb

  • Hi Tim,

    I followed your recommendations: I shorted the input voltage (VG1) and keep the DC voltage (V1) at input of op amp.
    AOlxbeta's gain is always negative, What is bad on my schematic?

    Remark: On the original design, I haven't shorted the DC voltage source V4. Were my simulations corrects?  

    Best Regards.

    Sylvain

    V_to_I_30_09_19.TSC

  • Hi Sylvain,

    I apologize, I forgot to state that a DC voltage needs to be added in series with R1 (in place of your input signal) to bias the transistor. The circuit, as it is now, will not work because the transistor is always off.

    To check to see if your circuit will work before running the AC analysis, we recommend to do a quick DC analysis to see if the output of the op amp is saturated to one of the rails. Doing this quick check can save a lot of time by avoiding unnecessary troubleshooting.

    So let me correct my previous statements. All AC sources (except for VG2 to run the stability analysis) needs to be replaced with a short, AC current sources replace with an open. A DC voltage may be needed to properly bias the op amp to put it in a linear region (prevent the output from saturating to one of the rails), like what you are using V1 for. A DC voltage may be needed to bias other components in the circuit so they operate properly.

    Thank you,

    Tim Claycomb

  • Hi Tim.

    Thank you for the clarification.

    Best Regards.

    Sylvain