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INA240: Sample phase

Guru 50955 points
Part Number: INA240
Other Parts Discussed in Thread: TL081, TMCS1100, TEST, TLV2461

8.3.1.2 Input Signal Bandwidth

The INA240 input signal, which represents the current being measured, is accurately measured with minimal disturbance from large ΔV/Δt common-mode transients as previously described. For PWM signals typically associated with motors, solenoids, and other switching applications, the current being monitored varies at a significantly slower rate than the faster PWM frequency. The INA240 bandwidth is defined by the –3-dB bandwidth of the current-sense amplifier inside the device; see the Electrical Characteristics table. The device bandwidth provides fast throughput and fast response required for the rapid detection and processing of over current events. Without the higher bandwidth, protection circuitry may not have adequate response time and damage may occur to the monitored application or circuit.

Q1: What technical Wiki leads datasheet to making (blue) and seemingly false narrative statement?

If that were entirely true then synchronous triggered ADC samples derived from PWM driven inductive events would be mostly seen as asynchronous to the hardware creating the events.

Q2: Could it be the limited band width (400KHz) has lead to an mostly incorrect deduction due to INA phase shifting of output events partially occurring outside typical ADC sample window? 

It would seem INA shunt calculator error % increases exponentially due to slower asynchronous current events if or when hardware attempts samples via a synchronous windows.

Q3: What modification to INA can be made to keep the output synchronous with PWM frequency events timing?   

  • Hi,

    Below is you’ll find answers following a copy of your questions:

    Q1: What technical Wiki leads datasheet to making (blue) and seemingly false narrative statement?If that were entirely true then synchronous triggered ADC samples derived from PWM driven inductive events would be mostly seen as asynchronous to the hardware creating the events.

    A1: The INA240 is an analog amplifier. The output is ideally an amplified version of its input. There will be phase delays but should be only noticeable at higher frequencies such as near the 3dB frequency and higher.

    Q2: Could it be the limited band width (400KHz) has lead to an mostly incorrect deduction due to INA phase shifting of output events partially occurring outside typical ADC sample window? It would seem INA shunt calculator error % increases exponentially due to slower asynchronous current events if or when hardware attempts samples via a synchronous windows.

    A2: What is “INA shunt calculator” referring to? The answer to this question depends on your system requirement, specifically the input (differential and common mode) characteristics and sampling speed/accuracy. Without knowing these requirements, the answer would be “Yes” and “No”

    Q3: What modification to INA can be made to keep the output synchronous with PWM frequency events timing?   

    A3: If the INA240 can reasonably replicate and amplify the input signal, it is up to the rest of the system and algorithm to keep synchronization.

    Regards, Guang

  • Guang Zhou said:
    There will be phase delays but should be only noticeable at higher frequencies such as near the 3dB frequency and higher.

    It would seem much like the TL081 Fig.8 significant phase shift occurs INA at lower 20-40Khz frequency. Without adding nearly 28,000 ADC clocks * (62.5ns) after a single 50us PWM event does the INA produce fairly accurate results above 2 amps. This phase shift create asynchronous SAR acquisition when it should be a CBC cycle by cycle PWM synchronous event. Again any Wiki that discuses current moves slower in the periods of PWM frequency? Such an assumption could be made by the way the INA output is most often out of phase with shunt input signal roughly 200µs. This also reflects back to sampling ADC as large and undocumented propagation delay. The case 9.6µs 0.5% of final value does not indicate amount of shunt precision error that occurs from ADC samples that occurs inside 9.5µs! Settling value of INA has nothing to do with input phase shifting relative to the source PWM that mandates and requires synchronous CBC samples.

    Guang Zhou said:
    A2: What is “INA shunt calculator” referring to?

    INA240 web page error analysis calculator for user input shunt values. ADC can't read INA below 7mA from even 25µs CBC purposefully synchronously delayed 100µs, this is not a deal breaker. However the top end samples via the same delay requires ADC re-calibration for PWM loads >2 amps. It would seem the output slew rate is often <2v via VS=3v3 especially during large CM differential phase shifting events. The initial transient response is excessive during phase shift periods. Thus it requires large resistance placed series INA output to counter measure current flow to/from analog channels charge share. That again introduces precison error beyond the INA error analysis calculator results for 2mohm shunt (below). 

    /cfs-file/__key/communityserver-discussions-components-files/14/6813.Total_5F00_Error_5F00_vs_5F00_Sensed_5F00_Current_2D00_-0.5A_2D00_50A-2mOhm.csv 

    Guang Zhou said:
    A3: If the INA240 can reasonably replicate and amplify the input signal, it is up to the rest of the system and algorithm to keep synchronization.

    At the expense of all precision that would other wise be 10x more accurate (CBC) via discrete amplifiers INA is touted to replace? Seemingly you don't comprehend the amount of INA precision error that occurs inside a 50 amp window samples <10 amps with 2mohm shunt. I estimate 32.7µs phase delay easily manifest into >200µs CBC sample precision error. How is that acceptable and why is there no TI work around of INA to correct such a huge precision error?  

  • Hi,

    Please show the input and output waveforms of the INA240 to identify the delay you’re talking about. This is the most direct evidence to support your argument.

    Alternative is to show the actual current compared with INA240 output. Remember to supply schematic corresponding to the hardware, and a picture of your setup as well.

    Once the delay is identified properly, it is then possible to address your other points.

    Regards, Guang

  • Guang Zhou said:
    Please show the input and output waveforms of the INA240 to identify the delay you’re talking about

    Oddly there is no frequency response graph to indicate output impedance changes can occur at certain frequency. Note the TL081 datasheet Fig.8 indicates high differential CM does cause 90° phase shift to occur 10kHz -1Mhz  even with 3Mhz unity bandwidth. Scope captures indicate random phase shifting >200µs and signal truncation occurs on any INA amplifier tested in several PCB. Please check your own trapezoidal PWM source and note the width of the analog output relative to PWM inductive source often is missing current periods. The entire output wave form is missing transient response periods (truncation) in the output 20kHz - 40kHz PWM frequency. That is the more alarming issue that can not be easily fixed input filter or not!

    Note the entire signal CH2 shift left/right from the trigger point CH1 (rising edge) and it don't matter what the input signal is doing. The output CH2 often truncates periods shifting what remains, left or right several periods relative to PWM synchronous time base of CH1. The output does not always remain locked to the input signal and phase shifts. Shifting causes large losses in ultra precision sensor from the ADC point of view - the only one that matters.  

      

     

    Guang Zhou said:
    Once the delay is identified properly, it is then possible to address your other points.

    This issue not specifically a delay, rather random phase shift from right to left and transient output truncation. Anyone can see with their own scope missing analog periods so plainly manifest. The differential amplifier appears to be squelching the input signal far to much. The INA in signal capture does not have 10 ohm Kelvin filter.  

     

  • CH2 INA output truncation (162µs) with CH1 rising edge trigger caught by Tektronix 2430 digital scope. 

  • Hi,

    We’re talking about INA240, and “delay” should involve the input and output of INA240.

    Comparing PWM edge with the INA240 output is comparing apple with orange at best before making sure there is no issue with the setup.

    Please refer to my previous post for what is being requested.

    Regards, Guang

  • Guang Zhou said:
    We’re talking about INA240, and “delay” should involve the input and output of INA240.

    We are more concerned with INA output phase shift relative to ADC sample period time frame and missing pulse information.

    Guang Zhou said:
    Comparing PWM edge with the INA240 output is comparing apple with orange at best before making sure there is no issue with the setup

    It seems you do not understand current measure must work as a whole from the ADC point of view not the INA propagation delay.

    The scope channels triggers alone can not determine which +/-IN (pulse period) belongs with which INA output pulse period. So the point is not of oranges rather only apples in that regard. 

    The only way to show INA phase shift occurs asynchronously when it should maintain synchronous pulse periods is from the ADC trigger source point of view, not the +/-IN input! 

    1. Please explain any datasheet graph showing INA +/-IN CM signals will never cause output phase shift (400Khz -3db) inside frequency range 10kHz - 100Khz?

    2. Please explain how the INA output open loop impedance never changes as a result of +/-IN bandwidth (400kHZ -3db) inside frequency range 10kHz- 100Khz?   

    It would seem you can not answer either question because there has never been such analysis relative to ADC synchronous samples. Dual time base scopes can ring out phase shift events but only from the SAR source triggering the scopes dual time base independently on each channel, ALT trigger mode.

    Your idea to trigger scope via +/-IN removes all reference of or to the ADC synchronous time periods relative to PWM triggered event being sampled. Both events have to be concurrent (synchronous) and they are not always keeping synchronous appear to phase shift relative to the ADC trigger. The ultra precision sensor is in no way maintaining any such precision but only to it's own reference. Period A must align with A sample and period B must align with B sample. When period A aligns with sample C or D the ADC and current algorithm see that as a phase shift in the PWM current loop!

    Perhaps one reason for phase shift being open loop impedance miss match. That is what TI engineering needs to confirm can occur by doing the very same check via MCU embedded ADC module triggered from the PWM source as it creates the inductive current envelope. The INA and the ADC must be synchronous partners, e.g. never shifting asynchronous in any way to the source of inductive current! Minor error is acceptable but this scenario is not minor error related

  • Hi,

    I’ll put it another way - how about comparing the actual current waveform with the INA240 output waveform? Is this a fair comparison?

    It should be readily clearly if there is a delay and further, how big the delay is. After all, INA240 can only try to amplify what it is being asked to (aka the input). If the input is truthfully presented to the output pin, its job is done.

    On the other hand, if the two waveforms show large delay as claimed, we can help figure out why and fix it.

    Regards, Guang

  • From current clamp versus the INA output and still will not show output phase angle changes relative a synchronous PWM trigger source shown CH1. How can we expect a bipolar input signal bottom half being stripped off in the INA output to maintain exact phase relationship as easily from mid supply REF? It will still be impossible to know how ADC triggered sample time differs from the INA output. Again REF mid supply has extremely course granularity little precision via the same Rs impedance match.  

    Datasheet infers 2 ohms impedance increase for every 10Khz frequency, 20Khz = 4 ohms. The ADC input sample hold impedance (3K5) relative 4k7 to 5k7 series resistor. ADC can also sample hold any Rs impedance <250 ohms 2MSPS but the signal must have series unity gain amplifier to match impedance into ADC Rs impedance to gain back lost precision. The INA contrarily to datasheet claim obviously is not directly compatible with SAR without added impedance matching. The same is true TMCS1100 extremely low output impedance again mismatches higher Rs impedance but adds CMTI @25kV/µs to stop rapid transients INA passes thus requires 4k7-5k7 series Rs to counter current fault trips. Otherwise without added Rs impedance the INA output clubs the MCU during rapid current rise crossing shunt CMV. That remains an random issue even with high Rs impedance 4k7-5k7. 

    The open loop gain (A1) should never peak >200mV (5amp) for steady state phase current (1.6amp).  The 2mohm calculated shunt 40mV/A and open loop gain wrongly peaks leading to phase shift of differential amplifier output via (internal feed back loop). The +/-IN signal has nothing to do with the phase shift as it originates inside the INA. Impossible to see random phase shift via +/-IN signals being the internal feed back loop drives the condition.

    Stacking 2 INA in series does not correct the impedance match issue though it does buffer the signal.

  • Hi,

    Your writing of theory is impressive, however I don’t understand it. I’m sorry that INA240 doesn’t fit; please find another device that works for you.   

    If you want to keep using INA240, then refer to my previous post, the request for information is still standing.

    Regards, Guang

  • Guang Zhou said:
    I’m sorry that INA240 doesn’t fit; please find another device that works for you.   

    How is that any kind of solution Guang?

    Might you try to answer the question of how the 240 can be made to work with SAR ADC to produce ultra precision current measures.

    It would seem you are unable or unwilling to test TI solutions necessary to fix this very broken IC. Especially since shunt transients easily pass through to the output club MCU thus requires adding excessive Rs impedance into the circuit. None of these attributes are speculated in the datasheet or errata document. 

    Note: The graph comes from the very discrete amplifier INA claims to so easily replace, how can that be? How is it you reject all this evidence and fail to present any graph to counter the possibility phase shift occurring. All you are attempting to do is discredit that which is submitted into evidence the output is not SAR compatible under all use cases. We are not going to spend hundreds of US dollars to design another PCB just because TI datasheet fluffs the facts and omits necessary information. Please take some time to review the datasheet and how the device is said to work as intended under all use case. 

    If you feel confident no such phasing of the INA output under any circumstance occurs please provide your evidence otherwise please help to find a workaround!   

  • Hi,

    Please provide input output waveforms of INA240, this will help prove whether INA240 is working or not. If not then we’ll look at your setup to see if there is a problem. All I hear so far is your complaint that your system is not working which can be due to a number of reasons.

    Regards, Guang

  • Guang Zhou said:
    Please provide input output waveforms of INA240, this will help prove whether INA240 is working or not

    The INA is working the best it can with what it has to work with internally. The INA will never work correctly with SAR ADC as it has been designed without a clue how it can achieve a proper impedance match with ADC!

    Please read below text how CMOS ADC requires a buffer amplifier. Yet most all TI sales marketing technical show INA with direct connection to ADC. Even older wiki INA connection pictures show direct coupling, makes anyone believe a proper impedance match is achieve by the INA alone. Perhaps ALL TI current monitor datasheets need to be revised with a foot note so others do not fall victim and make direct open loop connection to CMOS ADC. Oh boy do we see phase margin losses in the direct resistive coupling to CMOS ADC.

    It seems the TMCS1100 has 2nd amplifier placed after the 1st differential amplifier. That may provide 1st amp +/-IN overload output transient protection above the 2nd amplifier rail, much like below buffer. The INA output now clings to the high rail during +/-IN overloads passing transients onto the output into the CMOS ADC. If we attempt to add any CF without the buffer amp, INA overload transients club the ADC and MCU locks up. 

       

  • Hi,

    Each situation is different. If your system demands external RC filtering as shown, you can certainly include it at the INA240 output.

    As the datasheet shows, it can drive up to 1nF directly.

    Regards, Guang

  • I read that as the output will not load circuit more than 1nf capacitance no sustained oscillation.  

    Guang Zhou said:
    Each situation is different. If your system demands external RC filtering as shown, you can certainly include it at the INA240 output.

    It not a matter of whether it requires, being the transient response of some A1 are much greater than others, they are not consistent. That was partially the cause for the phase margin difference and missing pulses in this capture above. Once I replaced this one INA the initial transient gain surge and margin error went away. I have seen this transient surge before and was told it was due to a series ferrite in the circuit. It seems there may be an issue with certain lots of INA or they are marked A1 and actually A2 or A3 devices.

  • Hi,

    Looks like you have some theory as to the cause of the issue. I can’t express my opinion one way or the other as I don’t have details of your system, but will be glad to provide assistance when possible, if needed.

    Regards, Guang

  • Guang Zhou said:
    Looks like you have some theory as to the cause of the issue.

    It would seem there is more than 1 issue to confront making for some interesting posts. Perhaps some of the phase margin error originates in other INA from adding large Rs impedance to stop PWM fault transients entering the ADC comparator circuits. One plan of attack involves adding buffer isolation Fig.3-35 but the SOP5 amps are so tiny. Datasheet calls for 10k series with non-inverting input to limit the current to 5mA to stop input over load in rail to rail amp.   

    Would be easier to place TSSOP8 amp onto the empty pads for added buffer Fig.3-35 shows. I want to prove impedance isolation can be achieved in this way. The first INA output 5-7k in series to second INA buffer to gain isolation to reduce Rs impedance <250 ohms into ADC.

    Any ideas how to achieve that buffer with a second INA monitor?

  • Hi,

    Regardless which route you choose, I suggest try to nail down the root cause, including making sure INA240 is working properly in your setup.

    To select an OpAmp with desired features and footprint, please visit our online catalog. After zooming in on potential candidates, if you still have questions, please create a separate thread that exclusively addresses this topic and post to this forum.

    Regards, Guang

  • The INA at times transports motor current kickback into the ADC locking it up. Therefore high Rs impedance was required to reduce transient current entering ADC. Tina shows only a slight difference in precision loss via 2mohm shunt, less via 3mohm shunt. The Rs AC impedance (181) ohms into AIN-0 of ADC via 1A IG1 . You have to remove the ohm meter or it adds to the transient results.

     Do you think a dual INA might achieve double transient suppression and act as low impedance buffer into ADC? 

  • Hi,

    I think I’ve seen you post similar schematic before and provided related feedback at that time, therefore I won’t repeat here.

    I’ll only comment on your current question “Do you think a dual INA might achieve double transient suppression and act as low impedance buffer into ADC? ” The answer is no, the INA can’t be configured as shown. You’ll need and opamp as a buffer.

    Regards, Guang

  • Hi Guang,

    The link proves valuable to all forum members coupling the INA to an ADC. Review TI recommend for ADC buffer with low offset, rail to rail, 6Mhz bandwidth. I might check for Tina model at this link too. Nice thing being TSSOP8 foot print adds an easy button for custom PCB designs. 

    Thank you for posting above link.

    http://www.ti.com/document-viewer/TLV2461A-Q1/datasheet/description-sgls0084235#SGLS0084235 

  • Guang Zhou said:
    I think I’ve seen you post similar schematic before and provided related feedback at that time

    Nope, never posted Tina model as buffer with INA or any other amplifier. Actually posted dual model where 1st INA output feeds into second INA Ref pin. Dual INA via 2nd INA ref pin did not reduce transients or improve phase margin error since 5k7 was still required into ADC. 

  • Excellent link to place in the Amplifier forum header.

    http://www.ti.com/tool/DIP-ADAPTER-EVM

  • Hi,

    Thank you for your feedback, this generic adapter board is very popular.

    Regards, Guang

  • Also tested A2 buffer (several on hand) and Tina shows even better results than using an A1 buffer. How is Tina showing such good results but two INA can't double buffer transients? I think the transient issue will still be present via the amplifier buffer but I can't know at this point.

  • The double buffer would be good for sales INA devices if TI can confirm how effectiveness to reduce shunt transients entering the ADC. Seemingly the second INA should improve the overall circuits phase margin at higher input frequency and add double +/-IN transient suppression. 

  • Guang Zhou said:
    including making sure INA240 is working properly in your setup.

    That was part of the problem with one of test bench PCB we were reporting. An intermittent shunt ground was found to cause higher level output as current increased. Soldered shunt ground several times along the way of replacing that single 240. Intermittent low side ground makes the 240 output reach near VS rail at times. That was not the case of our custom PCB test bench. The added buffers on 240 outputs did seem to produce better comparator fault isolation, 240 could not alone achieve. So a rapid transient rather than simply clubbing MCU into POR would instead trip the fault comparator as expected. Left in place 5K6 between 240 output to TLV2461 +IN and coupled output via single ferrite chip to ADC inputs and analog comparators. 

    Tina analysis plots indicate the 240 can buffer similar to TLV2461, perhaps with even better transient isolation being expected.