This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PGA116: PGA116 spi sequence code

Part Number: PGA116
Other Parts Discussed in Thread: PGA117, OPA2314

Hello Everyone,
In a project related to acoustics, I should select sequencely 10 microphone pre-amplified and be able to change thier gain.
I found the pga116/7 which seems well suited to do this.
But i've some trouble to make it run with the spi interface.
The sequence code i sent are : (see table 3 page 29 of datasheet)
0x E1F1     (225 241) - Shutdown Enable circuit
0x 2A20     (42 32) - Write select Ch0, G=4
0x 2A20     (42 54) - Write select Ch4, G=32
0x E100     (225 0) - Shutdown Diseble circuit
But i don't get what i expected.
Any help gratefully received!
Many thank's in advance

Romano

  • Hi Romano,

    Are you running SPI Mode = 0, 0?

    The SPI Serial Interface Timing Diagram is shown in the image below. 

    Your SCLK signal looks different. I'd expect that it should be continuous for 2 bytes data, the clock is shown a gap between E1 and F1 when data sent.  

    CS-bar signal stays low after 2 bytes of data, see the image below. 

    If you are in Mode=0,0, the falling edge of CS-bar signal should align with D15 bit, which is high for E1. 

    The sequence code i sent are : (see table 3 page 29 of datasheet)
    0x E1F1     (225 241) - Shutdown Enable circuit - looks ok. 
    0x 2A20     (42 32) - Write select Ch0, G=4 - looks ok. 
    0x 2A20     (42 54) - Write select Ch4, G=32 - 0x2A54 ( typo)
    0x E100     (225 0) - Shutdown Diseble circuit - looks ok

     

    Please try it again and let us know. 

    Best,

    Raymond

  • Hi Raymond,

     

    Thank you for your fast reply.

    Yes, my SPI is running 0,0.

    I know my SLCK is a bit different, my spi interface send two packs of 8 bits separate by a gap.

    But this works (see screen shot below), write sequence and Read sequence.

    I just realize that I’ve misunderstood the shutdown command.

    First, we have to send 0xE100 (to wakeup) and not 0xE1F1 (witch put the circuit in sleep mode)!!! Ok, now it's very clear

     

    Write change gain


     

    Read


     

    But, I had also found another problem with the reference voltage.

    In my application, the 10 pre-amp are made with transistor stage.

    They can have an operating point dc which can vary from 1.3V to 1.9V maximum.

     

    If I connect Vref to a reference of 1.6V (Vcc/2), the PGA amplifies ac signal and of course also the difference dc voltage between input stage and Vref.

    That can be 0.3V times gain (at high gain, Vout will stuck at rail).

    Is there a downside to using the amplifier of the PGA in AC mode only as shown below? That works, but is it the right way?

    So, only the AC is amplified and the DC at the output follows the DC of the input.

     


     

    Thank you in advance for yours advices.

    Romano

     

     

     

  • Hi Romano,

    Question:

    Is there a downside to using the amplifier of the PGA in AC mode only as shown below?

    Answer:

    The Vref or pin 8 on p.4 of the datasheet indicated that "Vref must be connected to a low-impedance reference capable of sourcing and sinking at least 2mA or to GND". The Vref sample circuit is shown in figure 72, see the attached image below. The Op Amp buffer will offer low impedance requirements, since Vref is below Rf and R1 and connected to CAL4 pin. So please remove 1uF capacitor at PGA_GND pin, and follow the circuit shown in Figure 72.

    In addition, the Vref voltage has to be a stable precision reference IC against temperature changes, drift and noise issues. If you are not sure, please connect the pin to GND. 

    Question 1:


    What is the impedance after Vout or Pin9? Since this is audio application, what type is the ADC after 100nF?  If you have a part number, please let us know. We can  help you to select the AC coupling capacitor or you can connect pin 9 directly to ADC as shown in Figure 71. 

    Question 2:

    PGA116 is zero-drift PGA with Mux Op Amp, which much Op Amp errors are nulled out in the IC (a chopper amplifier internally). I am wondering about your ac signal of 100kHz from 1.3V-1.9Vpp  at Vcal/CH0 input. I speculate that you want to calibrate out the ADC Gain and offset errors.  The calibration hardware configuration is shown in Figure 72 with Vref=AVdd/2. Figure 71 is shown calibration configuration with Vref=Ground.  

    The system calibration using PGA is shown in Table 10 with Vref=AVdd/2. The system calibration is a DC calibration with the system's ADC, see the attached Figure 73. Figure 73 is shown 12bit ADC vs. Analog Input, which is Vref is configured at 1.5V and ADC_ref is configured at 3Vdc, see Table 10 and Figure 72. Table 9 is shown calibration example with ADC_ref=2.5V and Vref=GND. 

    Comments about Frequency Response vs. Gain:

    PGA116's full power bandwidth is the highest frequency that a sine wave can pass through the IC for a given gain, see section 9.1.3 and Table 8 of the datasheet. The Table 8 is obtained with load of RL=10kOhm and CL=10pf at Vout pin, see Figure 71. For audio application, PGA116 offers plenty BW. We just need to verify that Vout's resistive, impedance and parasitic capacitance at ADC as load, which it needs to be stable without oscillation per your audio application. If ADC is not used at Vout, we need to verify the load requirements for a different application. 

    10 Microphone input configurations are shown below: 


    Your microphone signals will be AC coupled to each input channel from Ch0-Ch9, see Figure 81. Figure  81 is shown two types of inputs, Ch0 is shown AC sine wave input. Ch1 is shown step function as input. In your case, you will need 10 identical input configuration as shown in Ch0. One thing I can't figure out is - why your input frequency is up to 100kHz (unless this is high frequency microphone). If  this is audio, it should have been between 20-20kHz approximately. Ca can be selected as 1/sC=X_impedance. At 100kHz with 100Ohm impedance in Ca impedance, (Ca can be calculated by the following equation), Ca=1/(2*pi*freq*100ohm)=1/(2*3.14*100kHz*100ohm)=15.9nf or select 0.1uf ceramic will do (impedance is at 15.9Ohm @100kHz). In Figure 81, Ca and Ra forms a high frequency pass filter. You can select Ca and calculate Ra for your high pass filter requirements. 

    If you need any other assistant, please let us know. 

    Best,

    Raymond

     

  • Hi Romano,

    I hope that your issues have been resolved.

    I am going to close this inquiry. If you have further questions, you may continue to post on the thread or open a new one. 

    Best,

    Raymond

  • Hi Raymond,

    Thank you for yor answers.

    In fact, I use this PGA as a line amplifierI (I probably missed to tell)

    Q1 : The output of PGA (pin 9) goes to serie of filter (conditionning) witch may have an input impedence of ~20kOhm.

    Q2 : The purpose of this scheme is not to calibrate the ADC input, but only amplifie the ac signal.

    Since there is a very small input bias current in PGA input (max 5nA), the difference dc voltage between Vref and Vin (with 100k for bias) would be around 500µV.

    Even with the gain max 128 (PAG116) or 200 (PGA117), the Vout dc will drift for a max of 100mV. So the ac signal remains centered.

    I've made several test and it seems to work well (now its very clear for me)

    If you agree with this, I'll consider that the case is closed.

    Many thanks for your good advices.

    Best regards.

    Romano

  • Hi Romano, 

    It looks good.

    Your input HPF has a zero at 33.9Hz (f=1/(2*pi*47nf*100k)=33.9Hz), I assumed that is what you want. 

    Q1 : The output of PGA (pin 9) goes to serie of filter (conditioning) witch may have an input impedance of ~20kOhm.

    Standard Op Amp does not like to drive capacitive load, which it may introduce an additional pole to create loop instability. Certain types of ADC may have this issue, that is why I am asking about impedance and parasitic capacitance at Vout. The attached circuit looks fine.

    BTW, I am certain that the PGA116 circuit is stable as shown. In case you have stability issues, you can reduce the capacitance by 10, and increase the resistor by 10, which you have not changed the location of zero in high frequency filter (Trick that I do in a circuit design). The same is true when dealing with a pole. 

    Q2 : The purpose of this scheme is not to calibrate the ADC input, but only amplifier the ac signal.

    Ok. In your high pass filter with OPA2314, the simulation is shown that there is Q at approx. 6MHz. I will get rid of the Q with another low pass filter prior to next stage (after OPA2314 Op Amp). I recalled that you are interested approx. 100kHz ac signal, and you want eliminate anything after approx. 1MHz. 

    Enclosed is the Tina simulation circuit in your OPA2314 HPF. 

    OPA314 HPF 03032020.TSC

    Best,

    Raymond

  • Hi Romano, 

    Do you want to provide me with input parameters at input stage? I was wondering if you have DC bias configured properly BJT's base. What is the impedance and capacitance of your crystal? What is the DC bias at circled point in red? You may have room to optimize the gain at the  BJT input stage.  Did you simulate this circuit?

    Best,

    Raymond 

  • Hi Raymond,

    The equivalent input capacitance is 10nF and the input resistance is about 20kOhm.

    Indeed the complete design already foresees an antialiasing low pass filter (50 KHz).  In principle I have no issues of bandwidth.

    My main concern is having the same reference DC voltage (1.65V) at input and output. Following the datasheet ratings, the PGA may generate 5nA DC current, which multiplied by 100kOhm, generates a 0.5mV off-set. In order to keep this offset as low as possible I can't reduce such resistance. I may try to reduce the capacitance by a factor 5 max to still satisfy my bandwidth constraints (fh is few KHz ). 

    Thank you again for your helpful advices.

    Regards,

    Romano 

        

  • Hi Romano,

    Your Op Amp BW  and remaining parts of the circuit look good. You should not have issues. 

    I was concerned about your oscillator, which it may have operating or self starting issues over time. There are many oscillator circuits out there (you may search images under google.com or via youtube.com). If you want to send me the oscillator tank circuit (L, R, C values for simulation), I can help as well. 

    Your input and output audio signals are AC coupled. Since you dc biased at the input and output, your AC signals will be running on the dc operating point (1.65V) .You should not have any issues there. 

    Best,

    Raymond

  • Hi Raymond,

    Thank you for your answer, but I don't think I have a problem with the input pre-amp.
    In fact, it is not an oscillator which must start by itself but piezo microphone which measures a vibration.

    Thanks again for your good advices.

    Best regards,

    Romano