Dear TI team,
I want to konw the role of R1 resistor below voltage follower circuits which is in the ti precision labs lecture about slew rate.
Thanks,
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Dear TI team,
I want to konw the role of R1 resistor below voltage follower circuits which is in the ti precision labs lecture about slew rate.
Thanks,
The small signal BW response is set by the loop gain. That is influenced by the R1 through the open loop output impedance in the model. Typically, adding R1 like 1kohm will improve phase margin and make the response less overshoot prone
However, 1kohm load is also sometimes modeling the probe load and, since you say slew rate, small signal is not part of the issue.
Hello Hyun woo Kim,
Is the resistor misplaced. I believe it should be in series with one of the two inputs. Some op amps have input to input protection diodes. For these op amp, some series resistance is needed for the slew rate test. Slew rate test applies a large input difference voltage.
Hello,
Unfortunately, your second and third image cannot be seen. You will need to try again to upload them if you would like us to see them.
From what I can see from the first image, the role of the R1 resistor looks to be simulating a load impedance. In the real world, there is likely to be some sort of load. A 1kOhm load was probably chosen because it is not low enough to significantly affect the output stage. For example, if the load impedance is too low it will significantly load the output of the amplifier.
Regards,
Daniel
Since you were apparently reading the slew rate info, there is a considerably more thorough discussion in these two articles if interested - most unity gain responses are 2nd order to start with, you can evaluate that response shape for peak dV/dT and then compare to device slew rate, this stuff applies to lower speed parts as well,
Part 16 goes on to how slew limited edges can extend settling times
Hello Michael
actually , I've checked reference circuits attached file.
That is simple voltage follower receiving PWM signal but R2 (10k) is connected inverting pin and I don't know exactly why it is connected.
so, I was studying ti's opamp lectures and found similiar circuits from slew rate lectures. then, asking question to TI E2E.
I'd like to simulate phase margin . Could you show me how to make test circuits ?
Thanks,
Hello Ron
actually , I've checked reference circuits attached file.
That is simple voltage follower receiving PWM signal but R2 (10k) is connected inverting pin and I don't know exactly why it is connected.
so, I was studying ti's opamp lectures and found similiar circuits from slew rate lectures. then, asking question to TI E2E.
Michael Steffes said this resistor is for improving phase margin and overshoot. What do you think about it ?
Hyun woo,
The R2 resistor is useless. However, it does waste electricity. It slightly improves phase margin in an inefficient way.
hi ronald
I'd like to simulate phase margin . Could you show me how to make test circuits ?
Thanks,
Morning Hyun,
I can set these up pretty quickly - in downloading the reference design, I see what has been a question for me as well - why do many of these parts specify a cap load in their spec tables or test circuits. They vary in value, part to part,
1. might be saying it handles Cload ok, but is it then implying that someone needs to add it to get the specified results?
2. might be saying the board and/or probe is going to have some, so include it
3. might be saying the mux or ADC inputs have it etc etc.
Normally, we do not do that in high speed but work with R loads of various values and deal with Cload through required isolating series R (parametric on gain, lately).
Ok, this was interesting -
The loading gets into the response shapes through the open loop output impedance.Apparently, that is quite high on this part,
The unloaded unity gain LG plot is here, very good phase margin to begin with, 77deg with 1.1MHz xover
With a 1kohm load, the LG=0dB xover pulls way back and phase margin improves 85deg with 520kHz xover
That says the closed loop gain of 1 bandwidth should pull way back with the 1kohm load, and (at least in this model) it definitely does, Sometimes that 1kohm is intended to capture the attenuating measurement path out to a 50ohm cable - that looks like a series 976ohm to a 51.1 ohm shunt to ground then into the cable then to a 50ohm scope or network analyzer - big attenuation, but no line bounces.
Oh and incidentally Hyun, this LG methodology and related issues were in these two articles,
The other possibility for those cap loads you see in the reference designs and datasheet spec conditions is to extend the bandwidth by reducing phase margin - that is described in figure 4 of Insight #5,
Here is the gain of 1 TLV9002 sim with a 100pF cap load added, yes, quite a bit higher BW but peaking in this case,
HI Ronald ,
is there any possible to reduce ringing noise of PWM edge ?
What do you think about it ?
Thanks,
With enough information, may well be able to square these up
Personally, I am thinking 3rd order of some low overshoot shape with an RC at the input and the unity gain buffer phase margin set to give the 2nd order part in the buffer - but would need
1. source impedance looking back
2. Voltage swing and supplies
3. desired max rep rate or rise times
4. load impedance
Dear Michael Steffe
actually , I've checked below circuits which is generating DC voltage with RC filter receiving PWM duty signal.
I want to know role of R2 (10K) but there is no any clue with TINA simulation.
it is just voltage follower output PWM signal. so, I supposed R2 is to reduce edge (rising/falling) ringing of PWM signal.
What do you think about it ?
Best and Regards,
Hi Hyun woo Kim,
as Ronald already mentioned, there's no need for R2. You can remove it from the circuit without any bad effect.
Kai
Well you have drawn this a bit oddly, but that R2 is on the output pin to ground and does get into the AC response shape through the open loop output impedance,
Since your post filter is so low in frequency, that effect will be filtered off and you can probably remove R2