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OPA2325: Open-Loop Gain Matching

Part Number: OPA2325
Other Parts Discussed in Thread: OPA2837


I'm looking to do a fairly simple transimpedance stage running at 10-20kHz, and I'd like to eliminate the error due to finite open loop gain, as far as possible. Datasheet shows typical OL gain of about 60dB at 10kHz so the transimpedance stage on its own will have an error of about 0.1% due to this. One thought I had was that I could follow the transimpedance stage (with its negative gain) with a simple buffer with x1 gain, which would also be handy for driving directly into an ADC input.

If I do this, I get that the transfer function (ignoring bias currents) to be:

If the open loop gains of the two amps are perfectly matched then the middle two terms in the denominator cancel and the effect of finite Aol becomes quite small. What I'm unsure about is just how well matched the gains of the two amps will be in reality. Since they're physically on the same chip I'd assume any difference will be small, but how small? At any given frequency, would there realistically be more than 1dB difference?



  • Gordon,

    The op amp open-loop gain, AOL, magnitude at any given frequency, fc, is a function of the gain-bandwidth product (GBP) where AOL=GBP/fc so at 10kHz, OPA2325 AOL = 10e6/10e3 = 1000 (60 dB). Thus, if you need higher AOL at a given frequency, you should simply pick op amp with higher GBP. Thus, for example, if you need AOL to be 80dB (10,000) at 10kHz, you need to use op amp with GBP = fc*Gain = 10,000*10,000 = 100MHz. 

    The issue of gain error at a given frequency has more to do with the variation in GBP than DC AOL.  Thus, your question is really pertaining to the variation in gain-bandwidth product, GBP, and not DC AOL.  GBP are never perfectly matched even between different channels of the same dual or quad package. The mismatch may be within 1% for parts coming from the same wafer lot BUT may be as high as +/-30% for parts manufactured several months apart due to long-term process variations.

    Also, your equation above uses a simple transfer function equation to calculate the gain error instead of magnitude equation. Using these equations will lead to incorrect results, specifically in the vicinity of the circuit’s cutoff frequency, where the actual error will be more significant.  The attached article shows how to calculate the closed-loop gain error for AC input signals at any given frequency.

    gain error.pdf

  • Marek,

    thanks for that info. Understood on the first bit about using amps with higher GBW, but I was hoping that what I proposed might give the better accuracy of a fast amp while avoiding the need for something with relatively high power consumption.

    On the second point, you're completely correct that the quesiton is really to do with matching of GBW. Where I referenced Aol, I meant gain at the particular frequency of interest - DC Aol is completely irrelevant for this application but of course, as you say, OL gain at my frequency of interest is entirely due to GBW. Thanks for the article on on accurately calculating gain error for any frequency.

    I'm now a bit confused. When you say that mismatch can be +/-30% from different wafer lots, does this mean that the two amps in a dual package are physically separate chips that are put together in the same package, and the two chips might have been produced months apart? My understanding was that duals and quads were generally fabricated on the same silicon die but happy to accept I might have that totally wrong.

    Following your point that it's actually matched GBW I'm interested in, I did a search for matched GBW in dual packages and one of the results was the following thread from this forum:

    The last post on the thread suggests good matching of AC parameters because layout is near identical and they're processed under the same conditions, which is what I would have expected. Bruce Trump's presentation in the PDF attachment (slides 35-39) specifically mentions that GBW is well matched in duals and quads. That seems to be in direct contradiction to your comment above.

    I might well be misnderstanding something here - any clarification would be most welcome.



  • Hey Gordon, 

    I think Marek was a little quick to put a +/-30% on GBP in a dual mismatch. I use the +/-30% number for part to part variation for "untrimmed" devices. Many of the higher speed parts have a trimmed supply current where I use a +/-20% GBP variation part to part since you have removed one of the variations with the supply current trim (that also tightens the slew rate spread, etc etc) 

    Duals are almost never separate die and with good layout they match pretty well on GBP

    I don't have a number for that, but it might be an interesting question for say a recent dual like the OPA2837

  • oh and incidentaly Gordon, I did do an example investigation of the effect of GBP variation on an active filter design in this recent article - this was in the context of establishing a min LG in the MFB design and then letting the model GBP vary. I went into the model and changed the dominant pole to do that in simulation.

  • Also if I look at the channel mismatch section of that really good10 little lessons slide deck it notes the mismatch based specs will not be any better matched on a dual than a single - that makes intuitive sense but I will say in working on the OPA2837 DC testing we were looking at trying to put a slightly tighter mismatch spec on offset voltage for instance than each channels offset voltage spread. Test data supported that but it wasn't much (15%) tighter than the single channel spec. There were certain applications that could have benefited from the best spec there, but all this was dropped in the final release apparently. 

  • Gordon, Michael,

    You completely misread what I said - here it is again:

    “ The mismatch may be within 1% for parts coming from the same wafer lot BUT may be as high as +/-30% for parts manufactured several months apart due to long-term process variations.”

    GBW=gm/(2*Pi*Cc) where gm~Itail (current biasing input differential pair)  and Cc is a Miller capacitance.  Since Itail and Cc may vary up to +/-15% due to process variation in sheet resistance and sheet capacitance, respectively, when they vary in the opposite direction these result in +/-30% variation in GBW from its typical value.

    But such mismatch can only occur in parts from different wafer lots.  Duals or quads obviously come from the same wafer lot so their matching of AC parameters like GBW is always within 1%.

    Parts manufactured several months apart may have GBW vary by as much as +/-30%  from their typical values:  this means that the GBW of OPA2325 may vary between 7MHz and 13MHz for wafer lots produced at different time BUT the GBW for channels of dual or quad will always be within +/-1%  because they come from the same wafer lot.  

    Thus, the max mismatch in GBW of two channels of OPA2325 may be:

    Typical 9.9MHz/10.1MHz

    Minimum 6.93MHz/7.07MHz

    Maximum 12.87MHz/13.13MH

    In other words, the absolute process variation in GBW may be as high as +/-30% but the matching within a wafer lot is within +/-1%.

  • Marek,

    that's a useful explanation. As I said above, I thought I was probably misunderstanding something somewhere and that explains it. +/-1% for GBW matching between amps in the same package intuitively feels about right, so that's a useful number for me to keep in mind in design. Your detailed description of where the variation between lots comes from is also helpful.

    Thanks for the clarification, much appreciated.

    Thanks Michael also for your comments, and the link to an interesting article.