On PGA280, does SPI use 8 bits, 16 bits?
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Section 7.5 of the PGA280 datasheet show the Command Structure and Register Overview to program the device.
Figure 52 and Figure 53 show the SPI timing diagrams for the read and write sequences when no Checksum is enabled. In general these are 16 bit sequences (except for the special CS mode where the GPIO extends the device communication to other external SPI device or when check sum is enabled).
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If I look at the waveforms in SBOA119 "PGA280 Communication via SPI", they all appear to be 8-bit waveforms. That is why I asked if it is an 8-bit or 16-bit SPI. Does the part look for 16 bits of information to come in? (2 8-bit bursts or 1 16-bit burst?)
The complete read or write SPI sequence transaction requires 16-bits.
CS must be held low during the completer 16 bit command sequence.
For example, the READ command:
1000 aaaa 0000 0000
The 1000 is the READ command, aaaa is the register address, and the number of trailing zeros provides the clock for reading data. At minimum, 16 SCLKs are required to complete the read data transaction.
On SBOA119, the microcontroller is generating 8-bit bursts, but CS is held low for at least 16-bit SCLKs during the SPI transaction sequences.
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