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LMP8350: Null DC offset for VOD?

Rachel Chaney
Prodigy 120 points
Part Number: LMP8350
Other Parts Discussed in Thread: TINA-TI, LMH6550, , THS4551

Hi, 

I have a LMP8350MA which I"m using to drive the inputs of a differential ADC.  I'm using this chip to convert from a single-ended input signal (DC - 1kHz) to differential.  

I am trying to remove a DC offset from my null measurement if possible.  My null measurement has: VIN+ - VIN- = -400uV. This results in VOUT+ - VOUT- = -1.5mV.  I've pored over the datasheet and cannot find the reason.  I think the gain is generally correct (unity gain), but there's a differential offset or imbalance.

I am using a 2nd order LPF from "Fully differential amplifier design in high-speed data acquisition systems"  which is a TI app note.  The differential gain of this system should be 1.  I've tried removing C26 and C30 on the offchance that they were causing the issue, but this change had no effect.

VOCM pin = 499.8mV, but output common mode is 501.3mV.  The common mode input is 499.6mV.  I am using a DC offset for the negative input because I wanted to prevent the DC offset caused by common mode mismatch, described in "DC Output Errors in a Fully-Differential Amplifier" which is a TI app note.  I'm not concerned really about the small difference in common mode inputs and outputs since they are subtracted out.  It's a little curious and I wonder if it affect my real problem.

I had thought the two paths were imbalanced since U2 and U13 aren't exactly the same circuit.  I couldn't calculate that this effect would occur with unbalanced input impedance.  I tested it out anyways, increasing and decreasing R15.  I found that this made a small difference to the VOUT- voltage (where decreasing R15 was a step in the right direction).  But it seems like the resistors need to change a lot to make a difference, so I think this isn't the primary cause of the DC offset in VOD. 

Using the calculations from that app note, I'd expected the DC output error of this circuit with this differential amplifier to be 200uV typical at room temperature.  What am I overlooking here?  

  • 0 in reply to Rachel Chaney
    TI__Mastermind 26805 points

    Hello Rachel,

       Thank you for the detailed explanation and extensive research using our app notes! I do not see anything too obvious from your schematic, other than the issue you brought up with the different source resistance. However, this probably would not cause a huge jump in differential like that as shown in your experiment. I will simulate your circuit on my end, it could be down to a stability issue. I will update you by Monday. In the meantime, what is the input source to the first stage, and just to confirm, you are seeing a measured voltage of VIN+ - VIN- = -400uV at the nodes STOD_N and STOD_P? 

    Thank you,

    Sima

  • 0 in reply to Sima Jalaleddine
    Prodigy 120 points

    Hi Sima, 

    Can't wait to heat about the results of your simulation.  

    Correction: -400uV was measured from INV_OUT to DIFF_GND.  

    R

  • 0 in reply to Rachel Chaney
    TI__Mastermind 26805 points

    Hello Rachel,

       Sorry for the delay in the update. I have set up your circuit in Tina-TI, would you be able to look it over and confirm the input and output voltages? 

    Rachel_DC_Offset.TSC

    Thank you,

    Sima

  • 0 in reply to Sima Jalaleddine
    Prodigy 120 points

    Hi Sima, 

    Thanks for this simulation.  I altered a few things to make it more like my application.  In particular, I added the DC voltages I measured on the nets by R1 and R4.  I reduced the size of the sine wave on VG2, so we could focus on the DC offset, and I removed VG1 (because that input is DC).  I also connected VOCM to the R1 voltage, as in the schematic.  

    I ran a transient analysis and found that the apparent DC offset on the VM1 is more like what I measured in real life!  There's a DC offset of about 1mV!  

    I've attached the edited TINA sim.  

    I feel like we're almost there!

    2148.Rachel_DC_Offset.TSC

  • 0 in reply to Rachel Chaney
    Prodigy 120 points

    Hi Simi, 

    I'm looking at the datasheet of the LMH6550.  I see it can be used to approximate LMP8350 in HP mode.  however, my application is using MP mode. 

    Also, the input offset voltage (differential) of the LMH6550 is typically 1mV.  About the same 1mV offset voltage from VCM.  I can't find them in the spice macro, but it's not an easy file for humans to parse.  i think this might be the cause of the 1mV output offset we see on VM1.  I've tried changing many parts and they don't make much of a difference to the offset.  

    The LM8350 datasheet claims +-80uV typical (+-2mV max) for input offset and +-230uV for VOCM offset. 

    This suggests the LMH6550 is maybe not the right approximation for this particular problem.  What do you think?

    R

  • 0 in reply to Rachel Chaney
    TI__Mastermind 26805 points

    Hello Rachel,

       Good catch on the input offset voltage in the datasheets. You are correct, that is unfortunately where the offset voltage is originating from. I will test the stability today and compare the bode graphs, and make sure it isn't a stability problem. From the small signal transient response (square wave), it would seem like it is stable due to little or no ringing occurring for this model. But, the phase margin could be close enough where for the LMP version, it might be unstable which is causing the offset to occur. 

    Thank you,

    Sima 

  • 0 in reply to Rachel Chaney
    Guru 140200 points

    Hi Rachel,

    the schematic is a bit confusing. Is this resistor 0R?

    If so, the LTC1050 could become instable due to the erosion of phase margin caused by C12.

    Kai

  • 0 in reply to kai klaas69
    Prodigy 120 points

    Yes.  That's a 0 ohm resistor.  What would the symptoms be for the phase margin issue you mention?  

    That seems unrelated to my problem of extra DC offset in the differential output voltage on U6.

  • 0 in reply to Rachel Chaney
    TI__Mastermind 26805 points

    Hello Rachel,

       I ran a stability analysis on your circuit, and it is stable (I have attached the Tina-TI below for your reference). I relooked at the datasheet, and even though it does say the offset voltage is typical at 80uV, the maximum is up to 2mV. This means parts with a offset voltage within 80uV to 2mV will pass our ATE. The part you have might have an offset voltage of 1mV, which is why you are seeing this extra differential offset. I could suggest another FDA that has a tighter offset voltage parameter (such as the THS4551 with a min of -175uV and a max of 175uV). What are your key amplifier specifications?

    Rachel_DCOffsetStability.TSC

    Thank you,
    Sima