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TLV7031: SPICE model bug doesn't allow floating bias

Part Number: TLV7031

Team-

The SPICE model for the TLV7031 contains various references to simulation ground ("0") within it. 

This prevents the model from simulating properly when V- is biased elsewhere from "0" (see example below).

For instance, here are just a few lines within the model that reference simulator ground:

V_V1         N332115 0 10m

I_I1         V+ 0 DC 315n 

R_R1         0 VOUT  1k TC=0,0 

Below is a circuit for an ultra-low power ideal-diode that is capable of operate over an arbitrary voltage range, not limited to 6.5V.

T2 provides the ideal diode function and T1 is a cascode transistor that protects the input of the TLV703x.  V1 represents a negative voltage regulator operating from the common-output of the OR'ing network.

In order to get this to work, I had to place simulator ground at TLV7031:V- as shown.  Very strange results occur if the circuit is grounded in the proper location "REAL_GND".  

I have included the TINA simulation if you would like to play with this.

Thanks, Best, -Steve

Ideal_diode.TSC