XTR115: Inquiry about New product and ESD

Hello Luis,

Thanks for your kind response.

I already recommended your guide to our customer.

I got their schematic and test condition/result like below.

Could you please review and get me your opinion about ESD?

* Test Result

Our device has damaged by ESD which condition is Contact 4kV, Air 8kV respectively.

* Schematic

* Test Configuration

Best Regards,

Michael

Hi Michael,

the schematic is impossible to read. Can you please give us a better version?

Also, where exactly was the ESD applied damaging the XTR115?

Kai

Hello Michael,

If you can please share a pdf file or a clearer schematic image showing the part numbers of the components involved.  

Please share the PCB board layout gerber files.

Also please clarify which part the circuit the Contact ESD 4kV, Air 8kV is applied respectively.

Thank you and Regards,

Luis

Hello Luis,

Thanks for your kind reply.

I requested PCB gerber file. If I get it, I will send it.

XTR115 was damaged by ESD. Another parts are no damaged.

Here is schematic.

If you can't see, please let me know.

Best Regards,

Michael

Hi Michael,

The protection circuit scheme used on the schematic above is different to the recommended on the TI reference design.

I am assuming that the ESD test is being applied at the Loop+ and Loop- terminal connections only.  Please advise if this is not the case and the ESD is applied at other points in the circuit.

In the Customer schematic above, diode D8 shows SMAJ28CA, a bidirectional TVS diode.  In the schematic above, there could still be a path for a relatively large positive voltage transient find a path through Loop(-) into XTR115 pin (4) Iout; and Iout should not be exposed to large positive voltage transients.  One suggestion would be to use a unipolar TVS diode D8 instead (SMAJ28A), to help limit the positive voltage transient and ensure IO is clamped (and avoid voltage inversions).

On the TI reference design, one key difference, a bidirectional TVS diode is followed by two ferrites on the positive and negative path.  These ferrites on both sides together with the supply c4 bypass capacitor to reduce high current transients into the rest of the circuit.  This circuit is also followed by a complete diode bridge to avoid any possibility of voltage inversion.  Please note the TI design still works even if the Loop + and Loop - are inverted due to the diode bridge.  The best recommendation is to follow the scheme below, as recommended on the TI design.  One further modification to the TI reference design below  is to replace D1 will be the 1.5KE36A that has a lower 49.9V clamp voltage and higher current rating for even more robust protection.

Thank you and Regards,  

Luis

HI Michael,

Thank you, let us know if you have further questions.

Best Regards,

Luis