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OPA2626: Settling Time in small signal space

Part Number: OPA2626
Other Parts Discussed in Thread: TINA-TI, OPA2837, , OPA837, OPA2625, OPA625

Dear TI community

I am developping and ADC stage with 16bit resolution and looking for a buffer to drive the ADC. The settling time is quite critical and unfortunately the graphic within the datasheet is pretty rough with 200ns/div. Is it possible to get some more information about the rising edge? I am looking for a graphic with 10ns/div to check if it fullfills the requirement. It would be used as unity gain in small signal space as well as large signal space.

Thanks in advance for your comments

Kind regards

  • Hello Claudio,

    Unfortunately don't have a more granular version of these plots, however can you clarify what requirements are you trying to meet?  


    Hasan Babiker

  • Hi Claudio,

    maybe a TINA-TI simulation can help?


    What ADC do you want to use? What is your charge kick-back filter?


  • Well Claudio, 

    At the physical level, it is critically important for good settling time to have Q<0.7 design and stay out of slew limiting on the transition, discussed some of this here, 

    Another device similar to the OPA2626 is the OPA2837. That device shows this simulated settling, note the input edge rates are controlled to stay out of slew limiting. Several decades ago, we used to try very hard to measure this kind of thing, that is so difficult, it has largely been abandoned these days, but if you wanted to see the best ever settling time with no thermal tail, look at the CLC402. And that plot is actually at the bottom of the article. 

  • So I went ahead and looked at the settling plot in the OPA2626, this is almost certainly a slew limited settling time, would be much faster if the input edge was slowed to stay out of slew limiting. Little history, 

    This is a dual, non-power control, version of the original OPA625 and OPA2625. At 2mA, it is perhaps only better than the 0.65mA OPA837 in input  noise. SInce I was doing the OPA837 datasheet, we stayed out of slew limiting on the settling set up - the precision amp guys doing the OPA625, 626 and duals apparently always allow their settling step to slew limit, which really hurts the performance. Also, that is not usually modeled very well so going to TINA will not help here. 

  • Not sure if I am allowed to say in a TI forum that I use an AD9266 ;). The charge kick-back filter is not defined up to now. I just want to make sure that the value is settled at the right time. As far as I read there, it needs to be half the clock cycle and with 20MHz it would be in the area of 25ns...

  • Thanks for your links and information, very interesting to read your article. I've read that its not really common to measure it that precisly nowadys because of the challenges that comes with it. This is why I am a little critical with simulating because you never know the accuracy of the model and how good the model is.

  • If you stay linear, the models have gotten pretty good - as I noted in the article, while slew rate is often modelled, not well enough at the fine scale settling levels required. 

    I have not looked, but is the ADI ADC differential input? If so, we normally use FDA's to drive it. Althought a dual op amp will do fine also and give you a high input impedance,