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TLV9062: Output voltage swing

Part Number: TLV9062
Other Parts Discussed in Thread: TLV9002, TLV9042, TLV9052, , ADC101S021, OPA2322, OPA2320

Hello team,

Could you please provide the output voltage swing (Vo) value for larger RL such as RL>1MOhms?

I'd appreciate if you provide the RL vs VO plot.

I'd like to check this in order to consider the limitation of rail to rail system.

The output goes to high impedance input, so I'd like to check the performance.



  • Figure 10 does not go down to 0 mA. But extrapolating the lines implies that the device can reach the ±2.75 V rails.

    The datasheets of similar devices like the TLV9002/TLV9042/TLV9052 do show 0 mA, and have a voltage drop of 0 V at this point.

  • Hello Itoh-san,

    Have I understood correctly: op amp output feeds high impedance and nothing else?  Could you please provide a schematic of the output so I can be sure to give the proper advice?

    The output of the op amp can come very close to the rails if you have the right conditions (light load current).  By very close I mean within a few mV.

    This subject is discussed in lesson 3 of this series of articles.  I recommend reading it if you have 5 or 10 spare minutes.


  • Hello Team,
    I really appreciate your quick response.
    I'd like to ask an additonal question to gain further understanding.
    At first let me provide a practical our schematic and a purpose behind our inquiry as below.
    1.Practical our schematic
     An op amp(TLV9062) is cofigured as negative feedback amplifier circuit.
      R1:5.1k  connects with "IN-" and ground.
      R2:120k  connects with "IN-" and "Vout".
      "Vout" terminal connects with "VIN" terminal of "ADC101S021(Vref=3.3V)": TI's ADC, directly.
      "Vin" terminal connects a input signal of swinging voltage from just about 0V to 0.6V.
     An amplifier Gain is 24.5 times
     Sigle-supply op amp configuration: "Vs"=+3.3V.
    2.Purpose behind our inquiry
     We would like to define as the maximum digital value of ADC output for an input signal saturated.
     And then we expect that the maximum digital value of ADC output is 1023(10bit), according to actual value of our schematic.
     However, we should consider the voltage output swing from supply rails of op amp at a former stage of ADC input.
     In other worlds, we would like to check the minimum value on the op amp swing to supply rails: saturated level conditions.
     According to technical document, VO is 20mV max.(VS=5.5V and RL=10kΩ), VO is 60mV max.(VS=5.5V and RL=2kΩ)
     I'd appreciate it if you could provide us with what a valid VO value on our schematic is. 
    Best Regards,
    Tohru Aramaki
  • The ADC's analog input has a capacitance of 30 pF; the datasheet says that it "will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance." The TLV9062 is such a low-impedance source.

    The ADC's analog input has a negligible leakage current, so the TLV9062 will be able to output voltages at the rails.

    The only possible problem is with high-frequency signals, because at the most extreme voltages, the TLV9062's output will not be able to (dis)charge the sampling capacitance as fast. See image 30, and note that it was measured with a load of 10 pF:

    What frequencies are you using?

  • Hello Aramaki-san,

    Thank you for the description of your circuit.  In addition to Clemens' comments, I would make a few of my own based off of your application.

    1. You should aim to have a precision from your amplifier that is comparable to your ADC.  This will ensure you use all the accuracy of the ADC.  In other words, the ideal total voltage error would add up to less than 1/2 the least significant bit of the ADC.  For example, if you have a 3.3V ADC with a 10 bit resolution, then you will want a precision of 3.3/(2^(10+1))V, or 1.6mV.  So, the offset voltage of the amplifier should be no more than 1.6mV. 

    However, you would also have to consider the gain of the amplifier which will also gain the input offset voltage.  Dividing by the gain of 24.5V/V, this would give us an input error of 65μV.  So, the large gain of the amplifier stage may require more accuracy from your op amp.

    2. Because of the feedback resistors, your load is actually not just the DC high impedance load of the ADC input.  The feedback resistors give you an effective load of 125.1kΩ in parallel.  As you approach GND, you will still be able to get an output that is very close to GND because the current through the feedback resistors will be very small.  However, closer to V+ there will be some margin.  It is not characterized by the data sheet.  However, the maximum DC current will be about 3.3V/125.1kΩ = 26.4μA.  This is still quite small so you should be able to get fairly close to V+, although I cannot say for sure just how close.

    3. One more thing that should be considered is that the input offset voltage will be gained and this will affect your ability to reach the output rail.  This will vary from device to device.  However, what may appear like an output limit can just be an output voltage error caused by the input offset voltage multiplied by the gain of the application.

    Hopefully this information is useful.  Please let us know if you have any more questions.

    Daniel Miller

  • Dear Mr. Ladisch,
     Many thanks for your additional explanation.
     The frequency is 166kHz we are using on it.
     I'd appreciate it if you could give a line-plot information of VS=3.3V case on the figure provided.
    Best Regards,
    Tohru Aramaki
  • I am not a TI employee, and that graph shows typical values. The knee for 3.3 V appears to be somewhere near 166 kHz.

    Is 166 kHz the sampling frequency or the signal frequency? Slower signals would work fine.

    If you need to handle 166 kHz signals, you should use an opamp with a higher slew rate, e.g., OPA2322 or OPA2320:

  • Dear Aramaki-san,

    The plot for the TLV9062 at 3.3V would look like the blue line below.

    As you can see, this is about mid-way between 100kHz and 1MHz on the logarithmic scale.  This corresponds to 316kHz.  We can also determine this using the formula below.

    Using this equation and the typical value for the slew rate of this part, we get a full-power bandwidth of about 313kHz.  So, your circuit will have the speed to provide the full output voltage swing at up to 313kHz.  Keep in mind that this assumes a few things:

    1. This is valid for a sinusoidal plot.
    2. There is no heavy capacitive load.  Heavy loads may affect settling time.
    3. This uses the typical value for the slew rate.  In the real-world, there will be some variation of this value.  So, it is a good idea to leave some margin.
    4. Most importantly, this does not take into account the output swing from the rail limitation.  This only accounts for speed and not output current/headroom capabilities.

    Also, Clemens has asked a good question: is this the sampling frequency or the signal frequency?

    Please let me know if you have any further questions.

    Daniel Miller

  • Dear Mr. Miller and Mr. Ladisch,
    I greatly appreciate your detailed description.
    At first I will respond to your question about frequency.
    The frequency of 166kHz is the sampling frequency, and a MUX(multiplexor circuit) switching frequency.
    At a former stage of op amp(TLV9062), it connects to MUX which comblines 16 original signal into one signal.
    And their signals are charged with a peak hold circuit in an approximately 250μs cycle.
    That is to say, the original signal frequency is around 4kHz.
    Now I share the beneficent information with my teams.
    If there are any question about that from my teams, I will get back to you soon.
    Best Regards,
    Tohru Aramaki
  • Dear Aramaki-san,

    I am happy to help.  As a final piece of advice, I would say that the general recommendation for amplifier speed is 40dB of margin between the open-loop bandwidth curve and the maximum frequency of interest into the op amp.  This is explained in detail in this app note (click here for link) and is summarized at the bottom of page 7.

    For example, the open-loop gain curve of the TLV9062 is below in red.  A gain of 24.5V/V corresponds to 27.8dB of gain.  So, with 40dB of margin, we would want about 67.8dB of gain in the open-loop curve at 4kHz (assuming this is the maximum input frequency of interest).  You can see that the TLV9062, which has a 10MHz bandwidth, seems to meet this metric.

    I hope our answers were clear.  Please let us know if further help is needed.

    Daniel Miller