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XTR111: XTR111: EF Pin Timing Implementation

Part Number: XTR111

XTR111: EF Pin Timing - Amplifiers forum - Amplifiers - TI E2E support forums

Hi Team,

I have question about the timing for Error Flag Trip. You could refer to the post in the above. I see that the delay time is about 665us. But this is result from EVM test. Does we have any doc explain on this. We want to make sure the wire break function. Do you have any recommend timing? Whether 3ms is long enough for EF trip for all condition? Thanks.

Best Regards,
Tess Chen

  • Hi Tess,

    the circuit of EVM does not seem to add any significant delay to the /EF pin. But consider the 10nF output cap (C3 in the EVM). The higher the output capacitance the more time the logic needs to detect the disconnection of burden, because the output capacitor will absorb a certain fraction of current that was originally intended for the burden. So I guess the total delay also depends on the value of output cap.


  • Hi Tess,

    We do not have characterization data for the timing of the EF pin over temperature or other conditions. The best data we have comes from Zak's testing in the post that you linked. The exact timing will likely depend on the circuit configuration.

    The error flag behavior is governed by the following (from this post):

    The circuit will operate properly as long as the voltage developed by the load does not reduce the drain-to-source voltage of the PMOS device to the point that forces it out of the saturated (active) operating region ( |Vds| < |Vds(sat)| ).  The maximum voltage on the source of the FET is controlled by the limits of the “IS” pin which are listed versus output current and ambient temperature in Figures 17 and 18 of the datasheet.  From there you’ll combine the IS voltage with the minimum Vds voltage specified for the FET to determine the maximum voltage from the positive supply that will still allow the circuit to operate with the desired current flowing.  If the calculated voltage is exceeded by the load then the FET will begin to get cutoff and the proper current will no longer be able to flow resulting in the /EF flag going LOW.

    Thus, the IS pin configuration used will affect where the cutoff point (and resulting EF trip) occurs. The timing of the trip will be determined by several factors. As Kai pointed out, when the wire break occurs the output will not immediately rail but will be slowed down by the output capacitance. This will result in a delay based on the RC characteristics of the output circuitry. This delay will cause the internal triggering of the EF to be delayed. Additionally, there will be a similar RC delay on the error flag pin itself that will be a function of parasitic capacitances and the external pull-up resistance used. On a scope this will look somewhat like a slew limit as the flag goes low, and will likely be largely negligible unless there is a significant capacitance on the pin. Finally there is the internal delay, which based on Zak's testing I would estimate is in approximately the ~600us range.

    Note that Zak's testing showed that a higher target output current results in a faster flag trip, and you can expect this trend to be observed in your application as well. If the customer's pullup circuitry and output capacitance are similar to those of the EVM then I would expect 3ms to be sufficient for a wire break trip to be registered. However, it's my recommendation that any customer concerned about the exact timing do their own testing with their final circuit. They can test the timing much as Zak did, by removing the load and measuring the trip time. Hope this helps!