• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 50 subscribers
  • Views 406 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM8272: Capacitive loading from input stage of ADS8568 is causing weird fluctuations I can't get rid of

PieterT
Intellectual 610 points
Part Number: LM8272
Other Parts Discussed in Thread: ADS8568, OPA2156

Hey everyone,

First time really going in depth with analyzing the oscillations/instability due to the input stage of a SAR ADC. At this point I've gone through about 3 buffers and now I'm using the LM8272 which should be able to drive any capacitive loading. Am I incorrectly simulating this or misunderstanding what the behavior should look like?

I'm posting images with the isolation resistance at the output of the buffer, however removing/adding it does little to the initial drop in output.

Here's the circuit. I'm reading in a clean 5V DC signal, followed by an ISA which conditions the signal slightly. This is followed by the buffer to drive the input of the ADS8568.

At the output of the ISA, small oscillations/dips are already present

The output of the buffer does not look great, I was expecting something a little more "steady". If this is normal behavior, an explanation would be very appreciated.

Lastly, here is the output of the buffer overlaid with the voltage of the SAR ADC's sampling capacitor. 

Am I missing something/ doing something incorrectly or is this not what this signal should look like.. Any help will really be appreciated

  • 0
    Guru 48395 points

    morning Pieter, 

    pretty much all SAR's recommend a "charge reservoir" cap right at the input to provide the initial charge transfer to the internal caps. You only show 5pF where most designs have maybe 1nF, once you add that, then the op amp stability requires a small series R. Oddly, for most op amps, increasing the cap at the SAR input reduces that required value. You might try a 1nF and 10ohm series R out of the op amp in sim. 

  • 0
    Guru 140200 points

    Hi Pieter,

    the EVM recommends this circuit:

    Kai

  • +1
    TI__Genius 15410 points

    Hi Pieter,

    These large dips are normal and are caused from the switching of the ADC. As Michael mentioned you may need to increase the output cap to reduce the dip and ensure that the output of the amplifier is settled by end of the acquisition period of the ADC. 

    I highly recommend taking a look at our TI Precision Lab Videos on ADC's. There is a lot of good information in there about designing a circuit, including, driving an ADC input and reference pin.

    There is also the Analog Engineers Calculator that will help you calculate the required output resistor and cap and the minimum op amp bandwidth the drive the ADC at a give sampling rate.

    Thank you,

    Tim Claycomb

  • 0 in reply to Tim Claycomb
    Intellectual 610 points

    Tim,

    Thank you for the recommendation on TI precision labs videos. It has been a great aid.

    In one of the videos they do go into detail about the minimum op amp bandwidth, however they only show the additional output resistor and capacitor reduces the required bandwidth but dont provide any formulas(except for the analog engineer calculator) to calculate said minimum bandwidth.

    Could you possibly point me to some literature or something that explains how to calculate the minimum op amp bandwidth requirement. 

    Thanks for all the help!

  • 0 in reply to PieterT
    TI__Genius 15410 points

    Hi Pieter,

    I'm not aware of any literature showing the minimum op amp bandwidth derivations. I recommend posting a question to our Precision ADC forum to see if they might know of something.

    Thank you,

    Tim Claycomb

  • 0 in reply to PieterT
    Guru 140200 points

    Hi Pieter,

    on the benefit of using a charge bucket filter Relaxed

    pieter_opa211.TSC

    Kai

  • 0 in reply to kai klaas69
    Intellectual 610 points

     thanks so much for going out of your way and providing a simulation model!

    I think my misunderstanding came in in that I believed the LM8272 didnt have a restriction on the capacitive load it could drive/ The datasheet says

    "The LM8272 is specifically designed to drive unlimited capacitive loads without oscillations (see Figure 25). In addition, the output current handling capability of the device allows for good slewing characteristics even with large capacitive loads (Settling Time and Slew Rate vs. Cap Load plot). The combination of these features is ideal for applications such as TFT flat panel buffers, A/D converter input amplifiers, etc. However, as in most Op Amps, addition of a series isolation resistor between the Op Amp and the capacitive load improves the settling and overshoot performance. Output current drive is an important parameter when driving capacitive loads. This parameter will determine how fast the output voltage can change. Referring to Figure 25, two distinct regions can be identified. Below about 10,000pF, the output Slew Rate is solely determined by the Op Amp's compensation capacitor value and available current into that capacitor. Beyond 10nF, the Slew Rate is determined by the Op Amp's available output current. An estimate of positive and negative slew rates for loads larger than 100nF can be made by dividing the short circuit current value by the capacitor"

    This was a misunderstanding from my end, however I'm currently looking at using the  OPA2156 and will add the charge bucket filter ;).

    Thanks again!