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OPA863: Inquiry on the total delay time to achieve 90% of Vcc

Rajat Jhunjhunwala
Prodigy 110 points
Part Number: OPA863
Other Parts Discussed in Thread: LM7171, OPA2834, BUF802, OPA2863

Hello TI,

I have been working on the opamp OPA863 and have a concern on the time delay to achieve 90% of Vcc. My application is high speed buffer.
My question is:
1: Is slew rate separate from rise time and fall time?
2: Is Settling time required when we are using the opamp as buffer?
3: Our input is ranging between 0 to 4V analog signal and Vcc is +5V. So if settling time is considered, what does the 0.1% mean? And for my application does it reduce evenly as % increases?

I have similar doubts for LM7171 and OPA2834.

regards,

  • 0
    Guru 140200 points

    Hi Rajat,

    usually, slew rate is a large signal parameter, while rise and fall times are low signal parameters.

    Whether settling time is important for you depends on application. If you want the output to follow the input step change in a certain period, then settling time is important. Assume you want to drive an ADC. Then settling time of OPAmp has to fall within the aquisition time of ADC.

    0.1% settling time means that the output settles within 0.1% of final value. This is 2mV for a 2V step. 0.1% means 10bit accuracy.

    Form the nature of settling, settling time cannot evenly decrease as the settling factor increases. See this link for a typical settling curve shape:

    https://en.wikipedia.org/wiki/Settling_time

    Kai

  • 0
    TI__Genius 17136 points

    1. Slew rate is a maximum edge rate, and usually dominates the "rise and fall time", which is typically the time it takes the output to reach 80% of the correct final value, in this case 9ns.

    2. Settling time is the time it takes for the amplifier output to reach a more accurate tolerance, in this case 0.1%.

    It sounds like you are interested in an accuracy somewhere in the middle.

    3. 0.1% settling for a 2V step means that for a 1.5V to 3.5V step, we measured that the output settled to 3.5V ± 2mV in 57ns. For a 4V step, it will probably take a little longer.

    You may be interested in the BUF802, which is a high speed buffer recently released by our product line.

    Best regards,

    Sean

  • 0 in reply to kai klaas69
    Prodigy 110 points

    My Input voltage signal band is 2.6%. So does this add the settling time in the total propagation delay of Comparator. 
    Note:- I don't have a filter at input or output. 

  • 0 in reply to Rajat Jhunjhunwala
    TI__Genius 17136 points

    Hi Rajat,

    The OPA2863 and the OPA863 should have the same behavior. The settling time of the output will of course be affected by the input signal behavior. What is meant by the following?

    Rajat Jhunjhunwala said:
    My Input voltage signal band is 2.6%

    -Sean