Amplifiers forum - Recent Threads

OPA2348-Q1: OPA2348 shorted

Donghyun. Kim — Tue, 21 Jul 2026 04:57:34 GMT

Part Number: OPA2348-Q1

Dear TI Technical Support,

We are currently using the OPA2348-Q1 in a 48 V PTC heater system.

We have encountered an issue where the OPA2348-Q1 appears to fail by becoming short-circuited, and we are investigating the root cause.

We would like to ask for your technical opinion regarding the following scenario:

The input voltage to the OPA2348-Q1 is present under normal operating conditions.
While the input voltage is still applied, the input Voltage(V+) connection is suddenly disconnected (open-circuit).

Could this condition potentially cause damage or a short-circuit failure of the OPA2348-Q1?

If so, could you please explain the possible failure mechanism and any conditions under which this could occur? Additionally, if there are any application notes or design recommendations to prevent such failures, we would greatly appreciate your guidance.

Thank you for your support, and we look forward to your response.

TAS5760M-Q1: TAS5760M-Q1 Open load detection

CHITHRAJ S — Wed, 24 Jun 2026 05:14:55 GMT

Part Number: TAS5760M-Q1

Hi,

I would like to know whether the TAS5760M-Q1 provides any built-in mechanism to detect if one of the speakers is disconnected (open-load condition).

I need to implement an open-load detection feature in my application. If the amplifier does not support this functionality internally, I plan to implement an external open-load detection circuit.

Could you please confirm whether the TAS5760M-Q1 supports speaker open-load detection or any fault indication for a disconnected speaker? If so, kindly share the relevant details or recommended implementation.

RE: TAS5760M-Q1: TAS5760M-Q1 Open load detection

CHITHRAJ S — Tue, 21 Jul 2026 04:44:34 GMT

Hi,

Could you please confirm whether the total shutdown current of the amplifier can be achieved at <10 µA with PVDD and DVDD in shutdown?

AMC3311: AMC3311 CTI (Comparative Tracking Index) Evidence and Supporting Documentation for Reinforced Isolation

Hori Shota — Tue, 21 Jul 2026 03:39:42 GMT

Part Number: AMC3311

Hi team,

Our customer is currently undergoing a safety certification review for an RF power supply that uses AMC3311.

As part of the review, reinforced isolation is required between the primary side and secondary side of the AMC3311. The customer is paying particular attention to the CTI (Comparative Tracking Index) value and understands that AMC3311 has a CTI of 600.

However, the AMC3311 certification documents available to us do not explicitly state the CTI value.

The customer would like to confirm the following:

Can TI confirm that the insulation material used in AMC3311 has a CTI ≥ 600?
Is there any official document, test report, certification report, or other supporting evidence that specifies the CTI value?
If the CTI value is not included in the certification certificate, could you share another document that can be used during the customer's safety review process?

Any supporting documentation or equivalent evidence would be greatly appreciated.

Best Regards,
Shota

OPA4325: Differential Input Voltage and Output Current (Source/Sink) specifications

Shuhei Goto — Tue, 21 Jul 2026 03:39:34 GMT

Part Number: OPA4325

Hi team,

I have questions regarding the following specifications for OPA325/OPA2325/OPA4325

[Differential InputVoltage]
What is the maximum allowable differential input voltage? Is there any condition or duration limit that should be considered?
[Output Current (Source/Sink)]
What are the typical and maximum output source/sink current values for these devices?

Best regards,
Goto

RE: THS4551: Gain Verification

Evan Kirkbride — Tue, 21 Jul 2026 03:39:33 GMT

Hi Nishant,

Apologies for the delay, I was out of office for a week.

On the general design considerations:

Thanks for the extra information on your input signals. I forgot that we were looking at square waves earlier. A 10MHz square wave worst case would need more bandwidth than the 10MHz filter scheme I proposed earlier as an example. You'll have to tweak what I do as needed.
80V/us on a 2.8V step --> 35ns rise time --> 0.35/35ns ~=10MHz at least required, however since it is a 10MHz square wave you'll want the harmonics to make a periodic edge clean.
16pF + 22pF only has ~9MHz of bandwidth. After playing around with values, I found that only having 2pF in the feedback and 1pF in-between the inputs gave the cleanest response in the time domain, no gain peaking with 60 degrees phase margin.

e2e.ti.com/.../THS4551_5F00_newlynew_5F00_schematic.TSC
e2e.ti.com/.../THS4551-newlynew-Stability-Eval.TSC
It's worth noting that a 30MSPS ADC may not see a 10MHz square wave very cleanly. You'll may want to consider 10X the fundamental frequency for bandwidth so 100MSPS at least in this case. If you end up going that way, you may want to consider the THS4541 as an ADC driver instead which is luckily pin-to-pin compatible with the THS4551 in RGT package.

On the board implementation and debug:

Probing IN+ and IN- pins directly is possible. However most probes introduce like ~10pF of capacitance which is going to change your results and stability conditions just from probing. It's ok to quickly double check things but just know your signals at that time will not look as good.
The 49.9ohm termination resistor could help you in your case since your signals are so fast, and it seems like you are using the coax cables and/or bringing different PCBs together. I would recommend a place holder before the Rg resistors to ground like R6/R7 below. With a 50ohm source you'll need to add a resistor the equivalent of the termination in parallel with 50ohms so ~25ohms.
With your 0ohm placeholders on the outputs, and the implementation of the FB pins, I think the schematic looks good other than the termination resistors on the Rg resistors.

On the TINA questions:

I'm not able to replicate your issues with converging on your TINA files. They run fine for me and the results look ok.
- It's worth noting on your piecewise linear inputs, your rise times are 10us >> 35ns needed for 80V/us.
THD isn't modeled in TINA unfortunately.
For noise, you can get the total integrated noise at each frequency by checking the Total Noise checkbox when running a noise analysis.
Gain margin can be looked at the same time as phase margin.
The THS4551 model was made before we started accurately adding Zo so the output loading doesn't affect the model much.
A manual break is better for stability analysis.

Hope this helps.

Thanks,

Evan

THS4551: Gain Verification

Nishant Gupta — Tue, 02 Jun 2026 19:58:49 GMT

Part Number: THS4551

I am using the THS4551IRGTT (16-pin VQFN package) as a fully differential amplifier to drive an AD9257 ADC. The ADC operates with AVDD = 1.8 V and provides a VCM of 0.9 V (AVDD/2), which is connected to the THS4551 VOCM pin. The THS4551 is powered from a single 5.4 V supply.

My resistor values are R1 = R3 = R4 = R6 = 1.2 kOhm and R2 = R5 = 3.3 Ohm in a single-ended to differential configuration. The input signal is a single-ended analog signal with a maximum amplitude of 2.8 V peak. I would like to keep the THS4551 differential output below 1.8 Vpp to avoid overdriving the AD9257 inputs.

Could you please confirm whether this resistor configuration is appropriate, or whether the THS4551 output will saturate with this input signal level?

I would also like to understand the role of the FB+ and FB- pins in this configuration and how they affect gain setting and FDA operation.

In addition, I would appreciate guidance on how to verify the design using TINA-TI or PSpice. Which simulations should be performed to confirm that the output common-mode voltage remains at 0.9 V, the amplifier operates linearly without clipping, and the differential output swing remains within the ADC input range?

Is transient analysis of OUT+, OUT-, and the differential output (OUT+ minus OUT-) sufficient, or are there other recommended simulations or measurements?

Finally, is it practical to validate this design on hardware using an evaluation board or prototype setup before committing to a PCB design?

OPA454: OPA454 status flag voltage

Ross McEwan — Thu, 16 Jul 2026 20:00:44 GMT

Part Number: OPA454

FIrst, I understand from other forum posts that the status flag is actually high when asserted contrary to data sheet section 6.

Section 7.5 of the data sheet specifies that in normal operation (i.e. negated) the status flag is a maximum of 2V above E/D COM. Later, in section 7.6, figure 24 shows how the voltage varies with temperature and pull-up resistor. These voltages do not make sense for either the negated or asserted state. If they are for the negated state they should not exceed the 2V from the table in section 7.5 (or section 7.5 should specifiy a pull-up resistance). If they are for the asserted state they are suspiciously low.

Also, the annotated pull-up resistors and currents in figure 24 seem wrong. If 50kohm gives 2mA, then 100kohm should not give 100uA.

I'm trying to interface eight ±12V powered OPA454s to 2.5V CMOS logic. It would be nice if this could be done with a standard level translator IC, but the specified 2V maximum in the negated state makes that impossible to do reliably unless I know more about how it's driven.

How exactly is the status flag pin driven in each state. It's a transistor to E/D COM when negated, but what is the resistance (or current) of this transistor? Presumably there is no strong drive when asserted, but is there a weak pull in either direction?

Thanks.

RE: OPA454: OPA454 status flag voltage

Ross McEwan — Tue, 21 Jul 2026 03:35:07 GMT

Your simulated circuit is almost exactly what I want to do, and I am confident a slight modification of it will work in my application.

I think my confusion was coming from the fact the data sheet specifies (on page six) output voltages for the flag pin when these are heavily dependent on the pull-up resistor and voltage. For example it specifies a minimum asserted voltage of (V+)-2.5V, which in the simulated circuit would be +50V-2.5V=+47.5V, but the simulation is obviously nowhere near that since the pull is to only +5V.

Thanks again for the very quick answer.

RE: TAS2573EVM-DOC-CERT: TAS2573 EVM no sound

zhou zhanshi — Tue, 21 Jul 2026 03:06:37 GMT

Hi Wenbi:

TAS2573EVM-DOC-CERT: TAS2573 EVM no sound

zhou zhanshi — Tue, 14 Jul 2026 09:17:18 GMT

Part Number: TAS2573EVM-DOC-CERT

My hand's tas2573 EVM based on the TAS2573 PPC3 setup,the spk no sound.please help check it.

RE: TAS2573EVM-DOC-CERT: TAS2573 EVM no sound

Wenbin Li1 — Tue, 21 Jul 2026 02:27:55 GMT

Hi Zhanshi,

get it.

in this case, we can close this thread currently. if you still meet new issue on new EVM. we an have another thread.

Br,

Wenbin

RE: TAS2573EVM-DOC-CERT: TAS2573 EVM no sound

zhou zhanshi — Tue, 21 Jul 2026 02:19:20 GMT

HiWenbin:

I have tried to use the U2 to do it,but still can't run and has the sound.The cfg file is load in the EVM maybe only support one U1 amplifier.I have ask the new EVM.wait the new EVM come on,I will keep continue to check it.

RE: TAS2573EVM-DOC-CERT: TAS2573 EVM no sound

Wenbin Li1 — Tue, 21 Jul 2026 02:14:35 GMT

Hi Zhanshan,

in this case, is it possible to use U2(tas2573) to do some test? if not, maybe you need a new EVM board.

Br,

Wenbin

RE: LMC7101: voltage value is greater than 1.04V

mao xiao jie — Tue, 21 Jul 2026 02:03:40 GMT

hello Ales,please help to confirm my below question again :

1.may i know what is the first change date code for LMC7101 serial caused by 20250129002.1

2.I noticed that in the changed materials, there will be a slash in the middle of A00B to distinguish between 0 and O. Are all the changed materials like this?

3.Are all materials with a slash in the middle of A00B considered the revised versions? If there is no slash in the middle of 0, it indicates that they are not affected by 20250129002.1

4.Will all the changed materials have the problem of excessive voltage? Could you please provide the daily test data and reliability test reports from TI?

LMC7101: voltage value is greater than 1.04V

mao xiao jie — Thu, 16 Jul 2026 02:28:20 GMT

Part Number: LMC7101

1.voltage spec :0.56~1.04 V,actual test is 1.477V and 1.475V , failure rate :100%,DC is 2618 and 2619 need to confirm the root cause,and if it can impact the function for LMC7101 serial

2.DC 2618 and 2619 made in cheng du ,related the PCN of 20250129002.1 ,There is a slash in the middle of body mark A008 to distinguish 0 from O. Are all the products produced from Chengdu like this with the body mark, or starting from the 2618 cycle, A00B will always have a slash?

3.what is the spec of voltage for LMC7101 serial

RE: OPA627: remove the trim pin in OPA627AU

Chen Alex1 — Tue, 21 Jul 2026 01:08:02 GMT

hi Carrie

we design the ICT for PCB test, we use many OPA627 in one board, need the trim pin to adjust the offset to lowest

if others device have trim pin, and spec same as OPA627

thanks

if no solution, we will change solution to others brand,thanks

OPA627: remove the trim pin in OPA627AU

Chen Alex1 — Wed, 15 Jul 2026 15:36:13 GMT

Part Number: OPA627

HI sir

we used the OPA627AU in many product, we need the trim pin to adjust the offset lowest in the system

also,OPA627AU have laser-trim , but still out of our system spec,

may i known ,which PCN Show removed the trim pin?

RE: OPA454: OPA454 status flag voltage

Carrie — Tue, 21 Jul 2026 00:25:33 GMT

Hi Ross,

I believe that Figure 24 is incorrect, thank you for pointing this out.

Below is the general statement on how to use the Status Flag pin.

The OPA454 features an status flag (Status Flag pin) that indicates two fault conditions (see below):

1. Overcurrent Protection: activates when output current exceeds the current limit (~150mA). In an output short-to-ground fault condition, the overcurrent flag asserts, which pulls the flag pin high.

2. Thermal Protection: When the junction temperature reaches approximately 150°C, the op amp output stage is in a high-impedance state and the status flag (Status Flag pin) is asserted, which pulls the flag pin high. When the junction temperature cools to a safe operating temperature, approximately 130°C, the output stage is enabled, and the op amp resumes normal operation.

This flag is an open-drain output compatible with standard low-voltage logic circuitry, such as a microcontroller (MCU). Choose the pull up resistor (R_P) value such that the pull up current (I_P) > 50μA. For example, if using ±50V supplies, set R_P = 1MΩ such that I_P = 50μA.

In the datasheet curves, the status flag pin was connected to V+ through a pull up resistor. However, the status flag pin can be pulled up to a separate external voltage if more convenient for application demands.

In Figures 47-49, you can see that as I_OUT reaches current limit (~150mA), the status flag moves from 0V to ~50V.

This behavior is also modeled correctly in the SPICE model. I have attached a quick simulation of the OPA454 with a current pulse output at 5mA and 1A. I set the status flag pull up voltage to 5V, and used a pull of resistor value of 10kΩ. You can see the status flag is low at the low current pulse, but gets activated high at the 1A pulse.

Please let me know if you have further questions.

Best regards,
Carrie

e2e.ti.com/.../opa454_5F00_status_5F00_flag_5F00_behavior.TSC

OPA211-HT: Forum ignored my message of "my issue not resolved"

nader niakan — Thu, 09 Jul 2026 15:18:54 GMT

Part Number: OPA211-HT

Hi,

During testing Vos and IB for my newly purchased op amps (OPA211-HT & OPA2333-hT), I observed that my measurments were way above the datasheet parameter values. I discussed that at the Forum and I tried to make my circuits per their recommendation. But, still did not reach the datasheet values. After going a few times bach & forth, I think Forum gave up on me and left my issue unresolved. I notified them twice about my issue left off unresolved, but they chose to ignore my messages !!

I wonder if a higher authority can call me at 805-304-9109 and discuss the matter with me ? We are working on an important high temperature sensor project and that is why I have selected these two op amps, among many other high temperature op amps in the market. Thank You

RE: OPA211-HT: Forum ignored my message of "my issue not resolved"

Chris Featherstone — Mon, 20 Jul 2026 23:17:02 GMT

Hi Nader,

The device appears to be unstable within your current test configuration, which is likely caused by parasitic capacitance from the long output cables. This capacitance can destabilize the op-amp, leading to the increased $I_{q}$ you are observing.

To demonstrate this, I have included an example below using an extreme case. Note that when the device is unstable, both the $I_{q}$ and the output voltage show unexpected results. However, by adding a 100 $Ω$ isolation resistor between the output and the cable, the oscillation is eliminated.

The 11mA $I_{q}$ measurement you are seeing is likely the average value captured by your DC meter during oscillation. To confirm this is the root cause, please try shortening the output cables or adding a series isolation resistor to decouple the output from the cable's parasitic capacitance.

Best Regards,

Chris Featherstone

RE: LMC6482: DAC output is not zeroing with Opamp circuit with follower circuit . 200 to 300mV output is coming without DAC out put ON also.

Alex Curtis — Mon, 20 Jul 2026 23:07:29 GMT

Hi Rama,

To clarify the design goals of the circuit, could you provide the input voltage range of the first stage, and the corresponding output voltage range of the second stage? What is the purpose of the overall circuit, and why is the offset adjustment needed?

With the adjustment set to 0V, where the +/-2.5V supplies are connected as shown in your circuit and assuming perfectly matched resistors, in order for the output voltage to be -200mV, either the voltage on the input is negative (not 0V), or the input offset voltage of the first stage is negative.

Due to the high gain of the first stage, if the input offset voltage of the first amplifier is -3mV and the input signal is 0V, the output voltage of the first stage would be will be approximately -63mV. See below:

This would be amplified by the second stage. If the input offset voltage of the second amplifier is also -3mV, the output of the second amplifier would be approximately -263mV with the adjustment voltage set to 0V, as shown below:

Also, even if the input to the second stage is 0V and the +/-2.5V supplies are connected, if the 10k+10k resistors aren't well matched on both the +2.5V and -2.5V legs, then the adjustment voltage will not be exactly 0V, even if the input offset voltage of the second stage is 0V. For example, if the top resistors are both 9.5k instead of 10k, and the bottom resistors are 10.5k (5% tolerance), this will result in -3.72mV at the output.

To summarize, the high gain of stage 1 is likely why you are measuring approximately -200mV at the output with 0V applied. Additionally, there will be error on the output from the matching of the adjustment resistors.

Best,

Alex Curtis

LMC6482: DAC output is not zeroing with Opamp circuit with follower circuit . 200 to 300mV output is coming without DAC out put ON also.

RAMA KRISHNA — Tue, 14 Jul 2026 07:36:02 GMT

Part Number: LMC6482

For these DAC out put nullfying ,

Now we want with Non Inverting OP Amp circuit with OFFSET Adjustment with Dual Opamp of LMC6482 circuit diagram.

Please share the circuit with OFFset Adjustiment circuit with Non inverting Opamp with LMC6482.

TINA-TI_ENGLISH: [LS ELECTRIC] Inquiry of TINA Simulation

Tommy Seol — Mon, 20 Jul 2026 08:59:59 GMT

Part Number: TINA-TI_ENGLISH

Hi,

My customer, LS ELECTRIC is trying to use the AMC1301 to divide a ±10V voltage by a factor of 1/40, receive it as a differential input, and then feed it into a DSP.

Customer performed a TINA simulation, but the results turned out differently from what they expected, so they have the following questions:

In TINA simulation, can different results occur when using different SPICE models?
There is no model available for the TLV9054 — do I need to input it separately?

RE: TINA-TI_ENGLISH: [LS ELECTRIC] Inquiry of TINA Simulation

Chris Featherstone — Mon, 20 Jul 2026 22:59:36 GMT

Hey Tommy,

Let us know if we can be of further assistance based on Ron's feedback.

Best Regards,

Chris Featherstone