Amplifiers forum - Recent Threads

OPA814: After replacing LT1812 with OPA814, the SFDR metric improved, but the INL metric showed progressive disease.

Jianzhou Li — Wed, 03 Jun 2026 01:31:53 GMT

Part Number: OPA814

When using the OPA814 as the output driver stage (TIA application) for the LTC1668 DAC, the SFDR result shows significant improvement compared to the LT1812 (SFDR is 66 dBc with the LT1812; SFDR is 82 dBc with the OPA814), but the INL specification has worsened. The design goal is to select an op-amp to replace the LT1812, achieving improved SFDR results without degradation in INL. Currently investigating the cause of the INL degradation. Is there a way to improve the INL result? Alternatively, recommend an op-amp that is pin-to-pin compatible with the OPA814 and offers better performance.

RE: OPA814: After replacing LT1812 with OPA814, the SFDR metric improved, but the INL metric showed progressive disease.

Jianzhou Li — Thu, 04 Jun 2026 01:51:55 GMT

hi Vikas Jeevannavar

The SFDR and INL results were tested on the evaluation board.
To ensure consistency of test conditions, the external test conditions for the LT1812 and OPA814 are identical, and the code used for testing is the same. Theoretically, the repeatability of the LTC1668 output is also fine. Repeated tests on the same platform yielded essentially consistent results (with a very small fluctuation range). Therefore, it can be concluded that the INL test results of the LT1812 and OPA814 show significant and repeatable differences.
The SFDR test method involves the LTC1668 with a CLK frequency of 50 MHz generating a 1 MHz sine wave signal, with the TIA circuit output amplitude at 2Vpp (the spectrometer test result is approximately 10.3 dBm). The INL test method involves the LTC1668 outputting a stepped DC current, which is converted by the TIA circuit into a stepped DC voltage.

After selecting the OPA814, the SFDR result achieved the expected effect, while the INL result showed significant progressive disease. Please provide your suggestions.

RE: INA180: ina180 with inductor dcr current sensing

Savit tipprecha — Thu, 04 Jun 2026 01:29:47 GMT

This is due to we need to improve eff for over all design so shunt resistor will most likely replace by DCR current sense. frequecy was fix at around 150k or 400k

INA180: ina180 with inductor dcr current sensing

Savit tipprecha — Fri, 29 May 2026 08:22:37 GMT

Part Number: INA180

Can INA180 use to sense output current in inductor DCR sensing method (voltage across Ccs) in conditon Vout = 12V , Buck controller = LM5148 ?

LMH6554: Design Issues of Cascaded CFB Fully Differential Amplifiers

cheng yang — Tue, 02 Jun 2026 06:44:15 GMT

Part Number: LMH6554

Dear Sir/Madam,

I have an application scenario involving small-signal amplification. I need to design a 4-stage cascaded CFB fully differential amplifier, with each stage providing a gain of 10x, and the signal bandwidth is 250 MHz. The preliminary choice is the LMH6554.
Can the interstage design refer to the circuit in the TIDA-00659 design document? Also, how should the interstage design balance signal integrity matching and the optimal output load of the previous stage, while also meeting the RF and RG resistance requirements of the next stage?
According to the circuit in the TIDA-00659 design document, the output load of the previous stage is only 100 ohms. If the optimal load for the previous stage op-amp is 1000 ohms, this difference is quite large. Or is it that the output load of the previous stage op-amp does not need to be given much consideration?

RE: LMH6554: Design Issues of Cascaded CFB Fully Differential Amplifiers

cheng yang — Thu, 04 Jun 2026 01:14:01 GMT

Hello: Thank you for your answer, it's very helpful. Next, I will do some simulations, build some test boards for debugging and verification, and see the actual performance.

THS4509: THS4509 : Can I get a s-para file for simulation in cadence environment?

Beomyu Park — Thu, 04 Jun 2026 00:31:26 GMT

Part Number: THS4509

Hi all

I'm using THS4509 amplifier to measure my DUT.

And i want to simulate my measurment setup in cadence environment.

To do simulation, I need s-para file of THS4509.

Can i get a S-para file?

thank you for your supports.

RE: LMH6554: Design Issues of Cascaded CFB Fully Differential Amplifiers

Evan Kirkbride — Thu, 04 Jun 2026 00:28:57 GMT

Hello,

Thanks for the information, very helpful. I don't think we'll be able to increase Rf greater than 300ohms then, if your input signal is controllable then a gain of 5V/V instead with 40-60ohm Rg would probably be preferred.

An alternative if loading really effects performance would be to impedance match in-between stages. Not really necessary if they are close enough but it does lighten the load by having the 49.9ohms in series. You just get the 6-dB drop in-between.

I actually think AC coupling would be better for general performance. However for something similar to LiDAR my understanding is that the pulse edge matters most so AC coupling will slow that down a bit, the exact value might have to be optimized.

I'll take a look and get back to you if I think any other device would give similar performance.

Thanks,

Evan

RE: LM158QML-SP: Stability testing and simulation of a -4.75V Discrete Negative LDO Linear Regulator Circuit that implements the LM158QML-SP

Art Kay — Wed, 03 Jun 2026 23:53:03 GMT

Elisa,

I tested the stability, but I didn't do it using the methods you recommended. I know the methods you recommended are commonly used in LDO stability analysis, but for op amps we normally use a different approach. Operational Amplifier Stability Theory and Compensation Methods covers this topic in detail. You don't necessary need to go through the document, but it is included for reference.
Also, I used TINA SPICE. As a TI employee, I am not permitted to use LT-SPICE according the the license agreement. I will post the schematics and simulation results below.
For hardware testing, I would apply a load step similar to the approach shown in TINA below.
Here is the DC operation of the circuit (it looks correct):

Stability can be tested by applying a transient load current step to the circuit output. This approach is documented in figure 8.3 of the stability document. The circuit responds with one large transient (step size), and one or more small transients (overshoot). For this circuit, I tested with a ±1mA step. The step size is 1.43mV, and the overshoot is 0.14mV. This corresponds to a 9.8% overshoot and a 59deg phase margin. A phase margin above 45deg is normally considered to stable, so this circuit is very stable.

Another approach to testing stability is to do an open-loop test. This test is documented in section 3.3 of the stability document. According to this approach, the phase margin is about 62deg. The step response shoed 59deg. The two results are reasonable close, and both are very stable.

Here are the source files:

e2e.ti.com/.../OP_2D00_AMP_2D00_LDO_2D00_STABILITY.zip

I hope this helps.

Best regards, Art

LM158QML-SP: Stability testing and simulation of a -4.75V Discrete Negative LDO Linear Regulator Circuit that implements the LM158QML-SP

Elisa Rodriguez de la Rosa — Wed, 03 Jun 2026 13:20:40 GMT

Part Number: LM158QML-SP

Hello,

In our project, we have implemented a circuit that is largely inspired by the design presented in your application note, "Space-Grade, 100-krad, –2.5-V, Discrete Negative LDO Linear Regulator Circuit." (chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/www.ti.com/.../slvaey8.pdf adapted the circuit to provide a regulated output voltage of -4.75 V from a -5.5 V input supply, and we are using the LM158QML-SP operational amplifier.

Now that the circuit has been implemented on our board, we would like to assess its stability using the invasive method, by injecting a small AC signal into the feedback loop through a transformer and measuring the loop gain of the regulator.

In parallel, we would also like to simulate the circuit and its stability in LTspice in order to correlate the measurement results with the simulation results.

In your application note, you provide loop gain simulation results for two output current conditions. Could you please indicate how these results were obtained? In particular, was the loop gain simulated by injecting a small AC signal directly at the non-inverting input of the amplifier, as done in the capture of LTSpice I shared with you? Using this approach, I obtain results that are similar to those presented in the application note, but not exactly identical, so I would like to confirm the methodology that was used. To be able to apply it to our desing.

Furthermore, when performing the loop gain measurement on the actual hardware, do you have any recommendations regarding:

The optimal location for injecting the AC signal into the feedback loop;
The placement of the measurement probes used to calculate the loop gain.

Thank you in advance for your help and guidance.

Best regards,

Elisa

THS4551: Gain Verification

Nishant Gupta — Tue, 02 Jun 2026 19:58:49 GMT

Part Number: THS4551

I am using the THS4551IRGTT (16-pin VQFN package) as a fully differential amplifier to drive an AD9257 ADC. The ADC operates with AVDD = 1.8 V and provides a VCM of 0.9 V (AVDD/2), which is connected to the THS4551 VOCM pin. The THS4551 is powered from a single 5.4 V supply.

My resistor values are R1 = R3 = R4 = R6 = 1.2 kOhm and R2 = R5 = 3.3 Ohm in a single-ended to differential configuration. The input signal is a single-ended analog signal with a maximum amplitude of 2.8 V peak. I would like to keep the THS4551 differential output below 1.8 Vpp to avoid overdriving the AD9257 inputs.

Could you please confirm whether this resistor configuration is appropriate, or whether the THS4551 output will saturate with this input signal level?

I would also like to understand the role of the FB+ and FB- pins in this configuration and how they affect gain setting and FDA operation.

In addition, I would appreciate guidance on how to verify the design using TINA-TI or PSpice. Which simulations should be performed to confirm that the output common-mode voltage remains at 0.9 V, the amplifier operates linearly without clipping, and the differential output swing remains within the ADC input range?

Is transient analysis of OUT+, OUT-, and the differential output (OUT+ minus OUT-) sufficient, or are there other recommended simulations or measurements?

Finally, is it practical to validate this design on hardware using an evaluation board or prototype setup before committing to a PCB design?

RE: THS4551: Gain Verification

Evan Kirkbride — Wed, 03 Jun 2026 23:32:05 GMT

Hi Nishant,

The FB+ and FB- pins are the outputs of the amplifier, brought to the other side of the package to allow for easy routing for feedback without having to go all the way around. This means the feedback resistors on pin 2 goes to pin 1 and pin 3 goes to pin 4. Your schematic will need to be altered then, the 3.3ohm resistors are currently in parallel with the 1.2kohm feedback.

I'm assuming the 3.3ohm is meant to be isolation within the feedback.

If your input signal is 2.8V peak, is that 2.8Vpp (+/-1.4V) or 0V --> 2.8V? That will help determine if your gain is correct to limit the output to 1.8Vpp for the ADC. If it is 2.8V peak I think the output will saturate you might have to attenuate it.

For simulation, I would have one to double check DC input/output common-mode voltage ranges and transient response for output ranges, can also be used to check frequency response. You can use this file attached for example:

e2e.ti.com/.../THS4551-Transient-Eval.TSC

However I would also check stability with this file attached. Here you can check loop gain and phase margin with whatever capacitive load or filter you might be expecting to drive the ADC. I would keep the split supplies here the model seems to react funny when you do a single-supply.

e2e.ti.com/.../THS4551-Stability-Eval.TSC

Hope this helps.

Thanks,

Evan

LMP8603-Q1: Minimum Gain Setting

Jessica Riley — Wed, 03 Jun 2026 23:12:33 GMT

Part Number: LMP8603-Q1

Hello,

I would like to use the LMP8603-Q1 current sense amplifier in a system which has a variable current range (0~25mA, -1.5A~1.5A). I would like to use the ability to reduce the gain by switching in the resistor from A1/A2 to ground. For the lower current range 0~25mA, it will keep the resistor disconnected so the gain is 100. For the higher current range -1.5A~1.5A, it will connect a 2.7kOhm resistor which should drop the gain to ~2.6 if my calculations are correct.

Is there any issue using the current sense amplifier in this way?

RE: LM358: Request Country of Diffusion

Alex Curtis — Wed, 03 Jun 2026 22:46:33 GMT

Hi Victoria,

To clarify, are you asking about Country of Origin (COO)? I apologize but I'm unfamiliar with the term "Country of Diffusion" specifically, so I would appreciate more details on what you're asking.

The original question you linked to states that "the part is exported to multiple countries including US, China, Japan, Germany, and others." The same is true for the LM358PSR.

Best Regards,

Alex Curtis

LM358: Request Country of Diffusion

Victoria Dai — Wed, 03 Jun 2026 01:10:05 GMT

Part Number: LM358

Hello, Would you help provide Country of Diffusion MPN: LM358PSR?

THS4541-DIE: DIe Pad Diagram versus xy pads locations

Ben Griffin — Wed, 03 Jun 2026 12:26:51 GMT

Part Number: THS4541-DIE

Hello, page 3 of the data sheet for the THS4541-DIE bare die shows a picture of the die and a table with x/ y locations.

In the picture PAD 14 is located higher than PAD 5 but based on the x/y data in the table PAD 14 is below PAD 5. Is the table data correct and there is a error in the picture?

RE: THS4541-DIE: DIe Pad Diagram versus xy pads locations

Ignacio Vazquez Lam1 — Wed, 03 Jun 2026 22:17:45 GMT

Hi Ben,

Sorry for the confusion. I was able to confirm the coordinates are correct so I would rely on that information and ignore the issue with the diagram.

Best Regards,

Ignacio

RE: TAS5825M: Time alignment of TAS5825m amplifier output signals

Isaac Buliva — Wed, 03 Jun 2026 21:47:28 GMT

Hi Marcelo,

What is the delta on the output signals that you are seeing? If I understand the question correctly, you want to be able to adjust a delay on your output PWM so that it is better aligned?

Regards,

Isaac

TAS5825M: Time alignment of TAS5825m amplifier output signals

marcelo vercelli — Wed, 03 Jun 2026 17:25:21 GMT

Part Number: TAS5825M

Hi there,

We have an amplifier design using four TAS5825m chips and fed by a TDM8 signal.

The board is up and stable and we have no audio performance issues.

The application requires "bit correct" alignement of the output signals and we noticed that we have differences on certain channels relative to time.

Is there any way to adjust the time delay on a channel?

We have searched inside Pure Path but didn't find a delay tool.

Our application incorporates a cross talk cancellation function and time arrival is critical.

Many thanks,

Marcelo Vercelli

RE: INA220-Q1: Query Part Specific Information via I2C/software

Louis L — Wed, 03 Jun 2026 21:44:23 GMT

Kyler,

Thanks for the question and using the E2E forum.

The INA220 does not have any identification registers like some of our other device.

A couple of other E2E threads with this same question can be found here and here.

Please let me know if you have any other questions.

Louis

INA220-Q1: Query Part Specific Information via I2C/software

Kyler Carson — Wed, 03 Jun 2026 18:45:22 GMT

Part Number: INA220-Q1

Hello,

I am evaluating this part for use in a new board design and need to be able to verify the authenticity/identity of the device via its I²C interface.

Are there any registers that expose a part number, manufacturer ID, lot number, or other unique identifier that can be read over I²C? I reviewed the datasheet but did not see any device-identification registers documented.

Thank you,
Kyler Carson

OPA814: simulate gain stability for ninv opamp

Dennis Brown — Tue, 26 May 2026 19:16:08 GMT

Part Number: OPA814

I have a design that uses the OPA814 configured as a unity gain buffer but it wants to oscillate when the feedback resistor is a 0 ohm short (the other resistor to ground being an open). It will stop oscillating once a 50ohm resistor is installed in the feedback. Seems there is limited phase margin here but I would like to know more about the analysis from tina. In tina, how does one simulate open loop stability or closed loop stability for an opamp configured in a noninverting format? Would like to see gain (dB) and phase margin (deg). Closed loop gain/phase is easier as this is what is in my tina file attached. There is nothing obviously wrong in closed loop format here to me.

There are a couple videos on the TI website that show similar concepts but not necessarily like this problem. If you have a link to something similar please post it. For the record the attached file does not show any sort of oscillation but I just want to know how to extract out gain/phase information under AC analysis so I have a better grasp on the problem.

OPA814_TINA_stability.TSC

RE: OPA814: simulate gain stability for ninv opamp

Ignacio Vazquez Lam1 — Wed, 03 Jun 2026 21:18:07 GMT

Hi Dennis,

The sim model might be overly optimistic on its ability to drive the capacitive load. In the device datasheet we recommended an isolation resistor of 50ohms into a 10pF load. I would assume 5pF would be in a similar range therefore little to no isolation will probably not work in most configurations. However since you have a PCB, we can focus on that to see what is happening. Can you share the schematic for the PCB you are testing. I am unsure what values are being used for the decoupling caps or surrounding components. In your PCB, are you removing any load when trying to debug the oscillation. I would recommend doing so to remove other variables.

Best Regards,

Ignacio

LM8261: Please determine whether it can be identified as an original authentic product based on the current information.

zhenhui zuo — Wed, 03 Jun 2026 03:21:25 GMT

Part Number: LM8261

The full part number is LM8261M5X/NOPB. Currently, there are photos of the die as well as front and back photos the device. Based on this information, can it be confirmed that the device is an authentic TI original?

RE: LM8261: Please determine whether it can be identified as an original authentic product based on the current information.

Carrie — Wed, 03 Jun 2026 17:43:18 GMT

Hello,

Can you confirm that the marking on the back is "51J"? Also, I can verify if the device is genuine if you have the original shipping information provided.

Best regards,
Carrie