TLV3011: TLV3011 Power Transition

Hi Russell,


Try adding a RC network between the power source and the 2 V+ pins, which should help to maintain a more stable power source for a bit longer time. Since the device quiescent current is low (<5uA), you could use a 2K resistor (<10mV drop) with a 10uF cap to the V+ pins.  Make sure that only the 2 V+ pins are connected to it.

If this does not help or not relevant, we can go a different route next.

Best.

-Jian Zhang
Apps engineer, LPAC PL

Hello Jian,

The following came in over a series of emails so I'll separate them with a --- so we're on the same page.  There's lots of info here to digest, so let me know if you need any clarity.

Thanks!

Russell

So we're on the same page, the precious shots were the supply voltage vs the REF pin, both pins 5 and 4 of both parts show the same behavior.  See pic 1 below.

The only change in supply voltage is when we go from battery power which could be as high as 3.7 to prime power which is down to 3V when the board is first powering on. And give the RC network a shot

 ---

Comparator_scope_captures.zip

There are actually two anomalous behaviors we're seeing with this comparator device.  There are two comparator ICs, one monitoring the battery for over-voltage and the other monitoring the battery for under-voltage.  Each comparator circuit may produce an invalid output state during a transition from battery-backup to local prime power.   These two separate behaviors may or may not be related (in terms of root cause), but they do generally exhibit themselves under that same condition in our system (transition from battery to prime power).  The bullets below summarize what we have observed thus far.  Sorry for the amount of detail, but I suspect it is necessary to share in order to fully understand what might be happening here.  

 

We're also including the oscope screenshots from the original email again in case you didn't get them forwarded to you.  These show the supply voltage input pin and the REF output pin (which you asked for in an earlier email).

 

 

This capture shows V+ which is in blue and REF which is in pink. A zip file is attached with more captures of the issues described below.

 

 

Common to both circuits/issues:

• · The anomalous behavior (comparator output briefly changes state) during the switch-over from battery backup to prime (local) power.
• · Each comparator is powered from the node that is switched between battery/prime power (i.e. the comparators' power pins see the voltage transition).
• · Each comparator's "IN+" input pin is sourced by an independent voltage divider from the battery voltage (separate divider for each comparator).  The divider resistors are large (100k or greater) and a 0.1 uF cap is at the input pin too.
• · Each comparator's "IN-" input pin is directly connected to its REF output pin without any bypass/stability capacitor on the REF output (as is shown in the datasheet's application circuit examples).
• · Each comparator's REF output pin has a significant response to the voltage switch-over transient that is subjected to the supply voltage pin.
• · While the poor line regulation of the REF output is very unexpected, it isn't surprisingly that it appears to be directly proportional to the transient's amplitude and frequency.  The transition from battery to prime power is both larger magnitude and faster slew rate than the transition from prime to battery power, and the resulting REF disturbance follows that.
• · Reducing the battery voltage results in the duration of the anomalous comparator output pulse reducing as well, to the point that a low enough battery voltage doesn't exhibit the behavior.  Presumably this is because the magnitude of the input voltage transient is reduced as the battery voltage is reduced.
• · Older revisions of the circuit card utilized a different battery switch-over circuit that switched over much more slowly (a few ms as opposed to 10 us), and these do not exhibit the disturbance on the comparators' REF pins.

Issue "A" (battery-voltage-HIGH monitor circuit)

• · During the supply voltage transition from battery to prime power, the REF output's disturbance has sufficient magnitude to drag the "IN-" pin's voltage below the "IN+" pin.  So in this case, the comparator is still fundamentally operating correctly as a comparator (nevermind the poor PSRR/line-regulation of the REF).
• · Adding a capacitor (0.1 uF) to the REF output reduced the disturbance on this pin enough to prevent the IN- pin from crossing the IN+ pin (disturbance was still visible, but small enough).
• · Summary of observable problem: supply voltage transients can disturb the REF output pin enough to drag the IN- pin past the IN+ pin, causing the comparator output to change state for the duration of the disturbance

Issue "B" (battery-voltage-LOW monitor circuit)

• · During the supply voltage transition, the same anomalous behavior is observed on the REF pin (it droops down, pulling IN- with it since they are connected).  
• · But in this circuit, the IN+ pin is at a higher voltage than IN-, so the droop on IN- actually pushes the comparator inputs further apart.  Despite this, the comparator output briefly changes state.  So even though the IN- pin's voltage was effected, it never crossed the voltage of the IN+ pin, violating the fundamental behavior of a comparator.
• · The addition of the 0.1 uF capacitor to the REF/IN- pin didn't change the anomalous output behavior (REF/IN- pins didn't droop much anymore, but the comparator output still pulsed to the wrong state for the duration of the supply voltage transient.
• · A 20k load on the comparator's supply voltage node (from a high-bandwidth active probe) results in the problem going away too.  This additional DC load does cause a bit of a voltage drop across series elements in the battery path, so maybe the battery voltage becomes low enough to reduce the magnitude of the switch-over transient sufficiently.  While 20k isn't much of a load, it is a lot more than the existing load on that node at that time.  This experiment was performed after adding the 0.1 uF cap to the REF pin, so it isn't known if this eliminated the other comparator's problem (since the cap alone was enough to do so).

So, as you can see, there are two separate problems that manifest themselves in two different ways.  At least one, if not both, of these issues result from voltage transients at the input supply pin.  The voltage transient we're subjecting it to isn't outside the datasheet ratings, so we're left wondering why the IC is behaving this way.  Regardless of what is in the datasheet, we need to understand whether this unexpected behavior is normal (even if unexpected) or anomalous (i.e. the parts we have are damaged or otherwise unique).  If this is normal behavior, we need to fix the circuit on our end.  If the parts are bad, then we need to shift our focus to figuring out how they're becoming bad (are we damaging them somehow or are they bad before we receive them?).  Does TI think these parts are acting differently than a "good" part, or is it likely that this is just the behavior of this device's design?  We think this is the first and most important question to TI at this point.

 

Regarding your request to put an RC filter in front of the comparator's supply voltage pin, I have some comments.

• · PSRR/line-regulation usually degrades with increasing frequency, and reducing the input voltage transient should reduce the output response transient.  We appear to observe that here.  
• · An RC filter on the input would also be expected to reduce the magnitude of (higher frequency portion) of the transient, so we'd expect the response to that transient to reduce as well.
• · Being as it is difficult to insert that series component into this circuit card and that we all agree on what to expect, we aren't going to bother to attempt to do so at this time.
• · To us, the bigger question is not can we make the transient go away (or smaller), but rather why does the IC have such a poor response to such a transient?
• · With that said, we do plan on building up a simple breadboard with this comparator to attempt to measure it's response to swept AC noise on its supply voltage pin (e.g. using a Venable FRA instrument).  We'll share what we find out.

---

 

Below is a plot of the REF pin's response to a sine wave injected onto the input supply voltage pin.  A Venable 350C was used for this measurement.  The measurement was repeated for multiple amplitudes of the injected sine wave, ranging from 200 mVrms down to 1 mVrms.  They all generally had the same response, with response peaking in the upper 10's of kHz to low 100's of kHz.  As the injection amplitude was decreased, the high frequency response generally degraded, suggesting some nonlinearity at play.  The datasheet's REF line regulation spec (that doesn't include a frequency point) of 10 uV/V (100 uV/V max), or about 100 dB (80 dB min), appears to only be realistic well below 100 Hz.  Regardless of that datasheet specification, is the response depicted below what we should expect from this device, or does this suggest this part is defective in some manner?  This measurement was performed on a breadboard with a "new" IC pulled from our factory's stock.

 

We're also attempting to characterize the the differential input voltage at which point the output changes state as a function of input supply voltage noise (injected sine wave amplitude and frequency).  This isn't quite as simple to instrument, so it might take a little longer to get good data.  Some preliminary manual measurements suggest that the device is definitely sensitive to give incorrect output states when subjected to frequencies near the peak of the curves in the plot below..

 

Hi Russell,

Meanwhile we're working on a lab prototype to duplicate the issue trying to get to the bottom of this. We'll get back to you with what we find shortly.

Best.

-Jian

Comparator Behavior.zipThank you Jian,

The following came in as well:

The Venable instrument made it really easy to measure the response of the REF pin to a signal on the V+.  The plot provided in an earlier email was measured at a supply voltage (on V+ pin) of +3.3VDC.  These measurements were repeated at 3.0, 3.6, and 3.9 VDC, with no discernible difference.  This applies applies to issue "A" as described in an earlier email.

With that said, measuring the analog inputs' sensitivity to supply voltage noise (issue "B") isn't as straight forward.  My initial thought was to set the supply voltage's injected noise (sinusoid) to a fixed amplitude and frequency, then slowly adjust the differential voltage across the inputs (using two bench power supplies) until the output toggles, taking note of the differential voltage at that point.  This would be repeated for various injected amplitudes and frequencies, which is a pretty painful manual process.

What I observed was mostly an "all or nothing" behavior.  By that I mean for a given injected amplitude/frequency, the comparator's output will:

• toggle (single transition) only when the analog inputs' voltages cross each other (i.e. normal comparator operation),

• pulse (two transitions) both at the beginning and end of the 100 ms sinusoid injection interval regardless of the voltage across the analog inputs (e.g. IN+ = V+ and IN- = V-),

• or, for a narrow range of injected amplitude before the onset of the latter behavior at some injection frequencies, the comparator output would toggle constantly or intermittently during the injection interval.

The fact that there doesn't seem to be any dependence on the analog inputs' voltages leads me to hypothesize that this mode of failure might be related to on-die coupling between a supply voltage net and a net related to the output driver circuitry (a net after the analog comparator circuitry but before the final open-drain output transistor).

Regardless of the actual root cause of the behavior within the IC, this behavior correlates well with the observed behavior in our system.  In issue "B" scenario, the output pulses (two transitions) immediately after the supply voltage transition even though the analog voltages are a few volts apart (REF node doesn't get perturbed that much).  When subjected to the Venable's sinusoid injection, we get a similar pulse on the output.  The pulses occur at the beginning and end of the injection internal, when there is an abrupt change from DC to AC on the supply voltage.  These sharp transitions at the onset of the sinusoid are very similar to the sharp transitions seen in-system when switching over from battery to prime power.  In the case of the Venable testing, the frequency of the injected sinusoid probably has relevance to the slew rate at that point discontinuity than the actual fundamental frequency itself.

Another nuance that was observed was a slightly different behavior of the output's faulty pulse at certain frequency/amplitude combinations.  In most cases that I tested (which aren't necessarily comprehensive, remember this is all manually testing), the pulse duration was on the order of 10-20 us.  But for relatively high amplitude sinusoids (400 to 500 mVrms) at frequencies around 500 kHz to a few MHz, the output pulse would be much longer (up to 30 ms or so).  Not only was the duration much longer than the "normal" case, but the beginning of the pulse was much later than normal too (normally about 10 us for 10-20 us pulses, but could be a few to a few 10's of ms for the wider pulses).  This becomes particularly relevant to us because one of our possible short-term solutions is to employ a SW debounce to mask this behavior.  We need to know how long these anomalous pulse could last, but there is a limit to the duration length we can ignore.  The testing performed to date is not by any means exhaustive, so we don't know (1) how long these pulse really could be or (2) if these much longer pulses could actually occur in our system (we've only observed these on the breadboard via Venable testing).

I attached a few oscope screenshots depicting different pulse widths for different injection amplitudes using a 500 kHz injection.  Note that there is a zoomed-in section on the bottom 3/4 of the screenshot that has either 20 us/div or 100 us/div, but all of these have 20 ms/div on the full capture at the top of the screenshot.

Hopefully this information helps narrow down the problem.

Hello Jian,
Any update here?

Thanks!

Russell

Hi Russell,

We're still working on it. Sorry about the delay.

Best.

-Jian