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Part Number: THS4524EVM
Hello, I am reviewing the THS4524 datasheet to the THS4524EVM schematics and I have a question. The first picture below is from the datasheet for the THS4524 and the second picture is from the THS4521 EVM. The output resistors R16 and R17 in the EVM schematic are not in the feedback path as they are in the datasheet schematic. Which schematic representation is correct? If they both are, can it be explained why?
Thank you for your time,
Hi David, Both the schematic representations are correct. The first picture from the datasheet implements a low pass filter along with differential to differential unity gain. The filter is implemented because of the 1.5nF cap and 50-ohm resistor in the feedback path. The second picture from the THS4524EVM implements only the differential to differential unity gain. As you can see, there is no feedback cap implemented. There will be attenuation seen at the measuring instrument due to the R16 and R17 resistors on the EVM, which will reduce the overall gain to be less than 1. You might want to look at the below link to understand working of an FDA: www.ti.com/.../sloa054e.pdf Best Regards, Rohit
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In reply to Rohit Bhat:
Rohit, thank you for your response. While reading the app note, page 22 and figure 28 show common mode filter capacitors at the input of the ADC. The app note states that the capacitors can be 2x the differential capacitor C3. The ADC that I will be using is the ADS1278-EP. That datasheet (page 37 section 6) recommends that the common mode capacitors be 1/10 the size of the differential capacitor. Which datasheet takes precedent?
Rohit BhatThe filter is implemented because of the 1.5nF cap and 50-ohm resistor in the feedback path.
Is that correct? Shouldn't it be 1k+49.9=1049.9 Ohm resistor in the feedback path to calculate the cut-off frequency of the filter?
In reply to dridgway:
In the app note, figure 28 shows the differential cap (C3) across the ADC to be broken down into two individual common mode filter capacitors of 2x value at the ADC input. So, you could either use the differential cap or the common mode filter caps.
In the ADS1278-EP datasheet, it says 1nF to 10nF should be used directly across the differential inputs - which is a must condition. Additionally, it says you could use a cap to gnd on each input which should be no more than 1/10 the size of differential cap (~100pF)- which is a may condition.
So the recommendation for the ADS1278-EP is that you certainly need a differential cap of 1nF to 10nF across its inputs - which cannot be broken down into 2x the value of common mode filter cap as the app note says. In addition to the differential cap, you could add a 100pF cap to ground on each inputs for any charge kick-back noise to be filtered out at the hold phase of the ADC clock cycle. To answer your question, the comment mentioned in the ADS1278-EP takes precedence.
In reply to Alexey Nikolaev:
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