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INA240: A2 REF1+2 RVRR 2uv/v

Guru 40090 points

Replies: 21

Views: 2419

Part Number: INA240

It would seem the datasheet analysis section leaves out very important factual info, REF1+2 divides A2 RVRR (2uv/v) effecting amp gain and noise immunity. Effectively lowers disclosed REF noise rejection and increases 50v/v gain to near 100v/v.

A 500uv/A shunt should produce 25mv/A in all disclosed REF configurations and actually produces 75 - 100mv/A when REF's are tied together. Tina INA240A2 DC or transient analysis macro is not producing correct output results for REF1+2 tied to external reference. Otherwise certain configurations of REF pins mislead customers in the design stage by plotting false data. Tina INA240 model is not disclosed as being DC model only and should produce correct transient analysis plot results for different configurations of REF pins and chosen shunt resistance values.

When REF1+2 pins are tied to an external reference the A2 50v/v gain nearly doubles, e.g. 50% error occurs as REF1+2 are below mid supply (+1.65v). Ideally we need to reduce REF1+2 below our +1.225v external precision reference to reduce output gain error %, not increase error as stated in datasheet, e.g. REF1/2 pins are above ground. 

That part of the datasheet as from our evaluation (REF1+2 external reference) violates Tina models and the electrical specifications section of disclosed amplifier gains. Perhaps lab can revisit the electrical specifications/analysis and total error sections to list WA for errata being disclosed?

  • In reply to BP101:

    Hello BP101,

    I am little confused as to how you are expecting 360mV at the output when your vsense is 4mV. Are you still using 1.225V for REF1 and REF2? For the test above, I did have a bypass cap for the supply, but no bypass cap for the Ref pins. From the standpoint of saying I want more rejection on my reference voltage pin, I agree that a higher rejection number would be better. However, our specification corresponds to the change in the internal input offset with respect to the change in the Reference voltage. Smaller RVRR means smaller internal offset change. Therefore a smaller RVRR is better.

    As for another debug measure, have you looked at just the INA240 without the ferrite bead, ADC, and comparator connected? I want to isolate these other devices to verify that the INA240 is the sole source of error. With the inductance of your ferrite beads and using one ADC with multiple channels, I suspect there may be some issues with crossover distortion.

    Best Regards,

    Patrick Simmons, TI Sensing Products Applications Support

    Getting Started with Current Sensing Video Training Series

    TI makes no warranties and assumes no liability for applications assistance or customer product design. You are fully responsible for all design decisions and engineering with regard to your products, including decisions relating to application of TI products. By providing technical information, TI does not intend to offer or provide engineering services or advice concerning your designs.

  • Guru 40090 points

    In reply to Patrick Simmons:

    Hi Patrick,

    After replacing A2 devices with A1 the SAR has better samples but up to 6amps (REF1+2 @1.224v) while dividing software any lower the fault comparator threshold must be set well above mid supply (2.8v). Just as many shunt transients occur INA outputs with 3v3 TVS diodes (1ns response) transients randomly trip comparator fault. There are no added filter caps on +/- IN pins at this time.

    Patrick Simmons
    However, our specification corresponds to the change in the internal input offset with respect to the change in the Reference voltage

    Not sure how one believes the words input referred directly mean internal offset. Neither RVRR graph states any such thing. 

    Patrick Simmons
    Smaller RVRR means smaller internal offset change. Therefore a smaller RVRR is better.

    However we are seeing a contradiction to that belief as higher RVRR of A1 is producing far less shunt CMM gain compared to A2. Yet A1 still has to high of shunt CMM gain relative to shunt uv/v value. It seems the INA is biasing the shunt since the output voltage is not consistent to +/- IN shunt peak, captured via X1 probe. However we could then via (A1) lower magnitude, software divisor get a much closer sample read via the SAR. A much thinner GUI scope widget trace (amps) is seemingly more evidence counters RVRR claim, less is more. It would appear from these real application test results (A1) the higher 20uV/V RVRR is somehow producing a lower shunt bias than A2 for the very same 500uv/A shunt.

    How can either INA (+/-IN) be changing the shunt bias relative to REF1+2 threshold for the very same shunt R value?

    Patrick Simmons
    As for another debug measure, have you looked at just the INA240 without the ferrite bead, ADC, and comparator connected?

    That is not possible in FOC motor commutation, all must report cycle samples to control PWM duty cycles and protect inverter from random faults via comparator reports. Oddly even with the lower A1 20v/v gain the comparator trip point was roughly the same threshold as A2 with REF1+2=1.224v  

  • Guru 40090 points

    In reply to BP101:

    Below are the scope captures A1 and A2:

    A1: @7.99-8.4 amps 500uv/A shunts, no input filter.

    Notice output peaks reach 2.7v near comparator fault threshold (2.877v) set very high and well over 10mv/A added to REF1+2=1.225v

    A2: 25mv/A output, 500uv/A shunt @7.99-8.4 amps. After below capture added 15n cap across shunt prior to switching to A1 monitors.

    Note REF1+2=580mv yet the output is nearly the same level as the A1 capture above.

  • Guru 40090 points

    In reply to BP101:

    Even with 1n or 200p caps in the output filter to SAR the gain of both A1/A2 have +1.225v REF1+2 added into the output gain. Notably even with output set mid supply (+1.65v) the A2 output gain had REF (+1.65v) added instead of being subtracted by the INA differential amp. Hence we had to restively divide the INA output to 540mv after being so confused by the bench results over 8 months ago.

    Indeed if TI lab tested the INA240 with 3 INA sharing the same REF via low side monitoring the same results should have been revealed from connecting the INA output into one of TI's SAR ADC's. Tina transient model is not showing these exact same test bench results. So the SAR is likely having some affect on the INA gain to include REF1+2 being incorrectly added back into the INA output gain.

    The REF1, REF2 voltages should only set the floor of the INA output and not be added into the amp gain. The first capture above post should peak @1.3v not @2.7v!

  • Guru 40090 points

    In reply to BP101:

    Should Ohm's law for multiple parallel branch resistors "Reciprocal of the added Reciprocals" be affecting REF1+2 sharing a single precision reference? Perhaps adding 100k in series each REF should invert the unintended reciprocals. Datasheet suggesting to set output mid supply VS/2 would be inflicted by Ohm's law as multiply INA might exist sharing the same VS power source.

    Note these external and higher R values too would be inflicted by Ohms law fowling INA output gain. On one hand adding 33R3k to each REF would simply cancel out, e.g. no net gain loss! The INA datasheet has not included any notice of REF gain correction formulas, let alone properly disclose strange phenomena being reported in this thread. How has this issue flown under the forum radar for so long, needs to be seriously questioned. Surely TI did not intend on customers circuit to subtract the REF from the INA output gain, wouldn't that be counter intuitive to what a current monitor does?
  • In reply to BP101:

    Hello BP101,

    You need to find a way to test isolated individual pieces of your system. There are potentially a lot of sources for error in your system. A few of these include:

    1. Layout – this can exacerbate EMI from high voltage switching and ground bounce
    2. ADC – can exhibit large transient if input source does not have sufficient drive strength or bandwidth. Multi-channel ADC also can experience cross talk.
    3. Excessive filtering – you are trying to measure a 12.5kHz signal at your ADC when the filters on your INA240 output appear to have a bandwidth in the hundreds of Hz, according to your recent post to Guang. This can potentially cause issues with your FOC algorithm.

    I recommend isolating one of your INA240 outputs and measuring to see what it looks like. Then I would recommend having your ADC measure only on one Channel with the other INA240 outputs disconnected from the ADC input pins. After each of those stages are verified to be working as expected or tweaked such that they are working as expected, I would then start integrating more stages of your system in. I know your inverter gates must be driven according to your FOC feedback algorithm. However I am sure there are ways you can impose 120 degree offset trapezoidal waveforms to your gates through a microcontroller or some function generators.

    If you do not attempt to isolate and verify your various system stages on the bench, it will be very difficult to fix your overall problem.

    Best Regards,

    Patrick Simmons, TI Sensing Products Applications Support

    Getting Started with Current Sensing Video Training Series

    TI makes no warranties and assumes no liability for applications assistance or customer product design. You are fully responsible for all design decisions and engineering with regard to your products, including decisions relating to application of TI products. By providing technical information, TI does not intend to offer or provide engineering services or advice concerning your designs.

  • Guru 40090 points

    In reply to Patrick Simmons:

    Patrick Simmons
    3. Excessive filtering – you are trying to measure a 12.5kHz signal at your ADC when the filters on your INA240 output appear to have a bandwidth in the hundreds of Hz, according to your recent post to Guang. This can potentially cause issues with your FOC algorithm

    Necessary to combat +1.225v REF being incorrectly added back into the output gain as the PWM duty cycle increases PWM rejection start to rapidly fail to stop any shunt transients >100mv from inflicting the INA output.  Large filter cap required so the SAR could have proper acquisition plus 880 ohm impedance.

    Guang's explanation does not hold up against scope captures showing SAR acquisition times 80us periods (12.5kHz) are indeed pristine! Also AC rms analysis is required to check SAR input impedance when PWM input signal used in Tina. DC analysis will produce incorrect impedance values. Note users must remove any Ohm meters from model prior to transient analysis or the plots will be infected via 1 volt applied into SAR.

    The problem is not with ADC or SAR, it is directly related to the INA configuration of REF pins and the voltage they are set to. Seemingly being confirmed by TIDA-00909 engineers example REF2 pin grounded sets A1 bias to 820mv and not 1.65v as table 2 suggested. Very likely they too encountered issue with REF which seems to have minor errata relative to how REF pins are being sourced from a precision reference. Why was REF2 tied to ground and did doing so make the differential amp subtract the REF1 input from the 5mohm shunt mV/A? 

  • Guru 40090 points

    In reply to Patrick Simmons:

    Patrick Simmons
    I would then start integrating more stages of your system in. I know your inverter gates must be driven according to your FOC feedback algorithm. However I am sure there are ways you can impose 120 degree offset trapezoidal waveforms to your gates through a microcontroller or some function generators.

    Patrick A2 was producing fair SAR acquisition REF/2 (1.65v), output being resistively divided down to 540mv via series 1k, 500ohm ground. The 500 ohm after the 1k pulled the gain down and aided REF from adversely inflicting output signal quality. There is undocumented behavior around the REF pins as they relate to the output magnitude without external input filters stopping EMI or PWM transients from inflicting the INA output, seemingly  >100mv. That part of the datasheet text astonishes a belief No input filters are required what so ever but fails to notify at what voltage level input PWM rejection might fail to stop shunt bound transients or otherwise EMI. It would seem the entire PWM rejection subject matter was produced mostly from inline phase monitor point of view.

  • Guru 40090 points

    In reply to BP101:

    Below capture INA output should appear similar at all PWM duty cycle speeds. This wave form (slower PWM duty cycles) quickly distorts seemingly from the INA input filtering blocking duty cycle changes in shunt current flowing the opposite direction. Perhaps 400Khz bandwidth is not adequate to keep up with the duty cycle changes of PWM generators and the signal becomes somewhat distorted as a result of duty cycle increasing speeds. Obviously the INA datasheet has voids in product disclosure of how to produce a proper balanced current signal at all PWM duty cycle speeds, not just at the slower rate.

  • Guru 40090 points

    In reply to BP101:

    Otherwise with little to no SAR filter compensation (1n or less) the ADC input more often sees low/high transient peaks. So the INA output has to be well below 1.65v bias and perhaps that helps INA to produce better ADC sample of the shunt current relative to SAR input filters, shown A1/A2 outputs. Perhaps these random peaks (below) are true current but impossible for the SAR to form ratio metric linear sloping from them. The compensated RC filter required for SAR settling inside sample acquisition times relative to lower input impedance mandate excessive roll off to achieve with the INA transient response times. Otherwise they cause random samples of overshoot in the detection of max level current mostly tripping faults on these peaks.  

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