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INA240: Output inversion
Part Number: INA240
Last thread posted scope captures confirmed 240 input polarity (+IN faces B+ supply) being correct and does not intentionally invert the A1 output. Yet any added external output filter quickly becomes saturated raising the open loop signal above REF, versus all negative CMV being produced below REF bias. The A1 output filtered initial balanced current wave form quickly becomes distorted PWM period pulses as the PWM duty cycle increases.
That is the least of what is going wrong as the output signal with no filters, output biased VS/2 (+1.65v) struggles to produce proper SAR full scale measure relative CMV of 500uohm shunt. The final results A1 output is unable to produce even 50 amp full scale for SAR of 1-2MSPS to 1/2 LSB. The 500mohm shunt with A1 gain is creating roughly 30mV/A output without any added input or output filtering of PWM trapezoidal waveform. Limited +/-IN filtering (10ohm, 1000n) reveals random phase reversals of negative current pulses being inverted above REF, again no added output filtering. This is an age old problem patched HW-WA only to come back and haunt our custom PCB upon re-examination to get precision above even 10 amps. Otherwise the output amplitude remains excessive no matter how REF is configured or filters being added or not added.
1. Why is the output signal A1 * 20 gain producing 30mV/A from 500uohm shunt with or without input or output filtering?
2. Why does connecting REF1, REF2 to ground not reduce the A1 peak output scale relatively?
3. Why does TI only seem to be testing complementary paired PWM signals or sinusoidal DSP with INA240?
4. How to make 240 produce proper SAR scaling from monitoring low side current flow derived from trapezoidal PWM?
5. Can TI engineers please test 240 with (trapezoidal) wave form low side monitoring 50-75 amp range?
BP101The final results A1 output is unable to produce even 50 amp full scale for SAR of 1-2MSPS to 1/2 LSB. T
Yet when the A1 output is conditioned via series 1K and 500R to GND the >30mV/A output solution reduced <10mv/A. So the 240 X20 gain acts more like X60 before output division pulls the signal down to X20. Why is the amplifier gain trim being required?
That issue tested similarly (A1,A2) devices indicates factory setting of amplifier gain being excessive in noisy PWM shunt conditions of low side monitoring. Rightfully a technical bulletin should be posted in forum to alert engineers of suspicious conditions devices being imported from 2nd party manufactures not holding intended specifications to 1st party certified documents.
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In reply to BP101:
Patrick Simmons, TI Sensing Products Applications Support
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In reply to Patrick Simmons:
Patrick Simmons4. We recommend starting with the design examples provided and understand that it may be an iterative design process following test and debug. Replicating unexpected or inconsistent behavior on a board completely removed from the application with more ideal lab equipment may be a good place to pursue debug
It ain't rocket science we seek! So it would seem the process being used by TI to set gain relative to shunt resistance is not holding true to industry typical and expected results of other manufactures devices that can and do. Other forum members report similar issues of excessive output gain on other INA devices. Now I read Patrick inform another forum TI employee the 240 has not 1 but 2 gain stages?
Patrick Simmons3. TI tests devices in many application conditions with both published and unpublished results. TI cannot test every possible application implementation for every device. TI guarantees device performance as specified in the data sheet electrical parameters table at the conditions defined therein.
However the 240 must conform to Ohms laws relative to shunt selection versus amplifier gain or the datasheet (summary) has little meaning. Datasheet claims 240 being good for PWM current monitoring and makes no distinction of specific gain class values changing as a result of specific types of PWM signal or placement of the device relative to CMV/CMMR in order to achieve said specifications. Suspecting at this juncture there is more to this story than being admitted in this forum setting.
Patrick Simmons2. Connecting REF1 and REF2 to GND changes the output offset such that the output should produce near 0V output with 0V input sense voltage.
Yet the datasheet specified behavior REF1/2=GND is not occurring thus indicates possible design flaw or other production issues are occurring outside those very testing parameters. According to datasheet text REF configuration too produces no output signal from shunt below ground CMV. Yet that level shift occurs below REF when specifically stated otherwise! It would behoove TI to do a full investigation on 240 device and determine why it fails to conform to datasheet circuit analysis in the various configurations.
Patrick Simmons1. Our devices are validated for gain error in our automated final test. If you put 2A DC across the 500µΩ shunt and do not see 20mV output above the reference voltage, then that is inconsistent with the data sheet and testing. If you input a sine wave, then you should see output attenuation consistent with figure 10 “Gain vs Frequency” in the data sheet
Yet the device is not being used with sine wave rather a PWM signal. So the entire frequency versus gain graph Fig.10 leads anyone to believe A1 maintains gain of 20 in the presence of PWM signal up to 100Khz. Besides the gain is more than 20 at -93db down from CMRR noise of (any PWM) signal according to Fig.10. Otherwise what you say is considered bait and switch tactic if any other signal besides PWM was being used in that process to achieve those graphs. Sure in perfect conditions girls in Australia don't wear swim tops at the beach but that don't make it prudent either.
Patrick Simmons5. We are not able to complete the requested test at this time.
If your supervisor was contacted to ask why our company was being made a victim in this scenario, might he/she give the green light to investigate rather than Patrick trying to constantly change the narrative of forum discussion to fit an unrealistic view point? Otherwise the other vendors device being functional under the same PWM conditions as the failing 240 being off boarded in photo below. It would seem all we are asking is/are simple questions and getting the run around by Patrick trying to deny culpability (comprehend situation) or produce any workaround to achieve the same results as other vendors product thus produces up to 100 amps with in 3v3 full scale SAR range. Surely there must be some area that TI can agree to take ownership datasheet opaque facts? Who knew sine wave was used to produce CMRR graphs or makes 240 work where overlapping PWM signals might affect gain. There is a difference between complementary paired and overlapping duty cycles, TI knows that.
Patrick Simmons1. Our devices are validated for gain error in our automated final test. If you put 2A DC across the 500µΩ shunt and do not see 20mV output above the reference voltage, then that is inconsistent with the data sheet and testing
Definitely is not producing 20mv @2amps and A2 in photo was closer to 190mv over REF for REF/2 or VS/2 (1.65v) @7.9-8.2 amps. That is an average peak, not peak! Will be testing A1 on the same Jiffy PCB (photo), input filter 10ohm + 100nf. Filter makes negative CMV invert above REF in random phase shifted pulses, no output filtering. Jiffy PCB has 6.8uf polymer electrolytic 0.1uf filtering +3v3 and not to far from 3v3 LDO (red wire) wrapped (blue) via digital GND, not analog GND.
The previous thread last test of the three A1 on motor PCB has REF1+2=GND via 49R9/100n filter (each A1), REF roughly 30mV above ground. Yet the output signal pulsed near 1v9 peaks, almost 1/3 full scale @8amps phase current even with 4K87 divider each A1 output. Far more than X20 gain was being produced by A1 output. Potentiometer rule confirms the output divider should keep signal well below 200mv. Tina transient analysis plots have no indication of increased amplifier current gain result of CMRR being 95db @12.5kHz PWM.
Our motor PCB circuit for A1 should be roughly 120mV-30mv REF output @8 amps phase current, not 1v9 especially after output division. Seemingly the shunt CMV leaks pulse voltage directly into A1 output increasing *20 gain via -CMRR creepage. Perhaps little to no EMI shielding in the 240 allows shunt crossing high frequency RF to increase amplifier current gain past any datasheet stated gains (A1,A2,A3,A4). Either way any improvement in A1,A2 precision is seemingly out of the question until the 240 architecture has been corrected to stop PWM creepage or shunt -CMRR migration into output signal. This behavior of 240 is a game stopper!
BP101Definitely is not producing 20mv @2amps and A2 in photo was closer to 190mv over REF for REF/2 or VS/2 (1.65v) @7.9-8.2 amps. That is an average peak, not peak! Will be testing A1 on the same Jiffy PCB (photo), input filter 10ohm + 100nf. Filter makes negative CMV invert above REF in random phase shifted pulses, no output filtering
Have discovered as reported above, EMI/RFI creepage or PWM intrusion of stated -CMRR (+95db @12.5kHz) is reduced when 240 located away from CMV of (shunt main PCB). Proximity of shunt answers why 240 placed vertical (jiffy PCB) to that of shunt orientation reduces almost removes all PWM intrusion (EMI/RFI) on A1/A2 output effecting open loop gain of any 240 mounted parallel (planar) on main PCB plane.
This output gain issue manifested obviously from lack of internal case shielding 240 amplifier. Hence there is a proximity ratio of CMRR based on shunt location to +/-IN pins not being disclosed in datasheet. This proximity issue obviously escaping any laboratory updates to datasheet is troubling to say the least. Forum guru post 8 months ago "TI was sending 240 out for EMI shield testing." Results of EMI testing has never been disclosed to public, forum discussion or Wiki updates as it should have been. Now we think Numetal covers are required to stop excessive open loop gain of shunt crossing -CMRR being exposed on A1 output via EMI?
Vertical mounting 240 above or locating package a specific proximity away from shunt PWM source reduces effect of planar EMI from attacking amplifier open loop gain. Where is that seemingly and relative fact being disclosed in 240 datasheet? Are we to just take these sour licks and like it or should TI investigate why or how EMI is so effecting datasheet culpability? We think they should step up to the plate and expeditiously rectify this issue ASAP for all 240 devices or at least manufacture a replacement 240 with full internal Numetal shielding!
Interestingly TIDA-00909 engineer added EMI phase filters during 40-100Khz PWM test runs A1 package and failed to report major effects of EMI on the open loop gain of the 240 amplifier output (unfiltered). Logically 240 does not require (external) EMI filtering +/-IN if the package was shielded or PWM rejection actually rejected CMRR of PWM as being depicted in Figure 12. The 240 open loop signal does seem to improve with faster PWM duty cycles (increase CMRR +db) in response. Yet CMRR rejection is a bit late to correct wild open loop gain in output filtering required to roll over peaks of huge EMI pulses crossing any shunt.
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