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TL082A: Design Voltage attenuator by a TL082A

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Replies: 14

Views: 529

Part Number: TL082A

Hi Team,

 Here is a application. A 1200Vdc should be attenuated to signal level and connect DSP A/D terminal. I'm learn the method there are:

 1. Using the passive resistor and consist a divided circuit, after series a buffer to DSP,

 2. Using differential input for OP ( TL082A, Set Gain 0.002 V/V) and series a buffer to DSP, 

 3. Using fully-differential amplifiers and series a buffer to DSP

 4. ... 

 My questions are:

 1. Weather have more solution for High voltage attenuator, how about each of solutions pros and cons?

 2. For cost concern, I'm try to use solution 2 (TL082A, ). Can you advice It's a good option or not? What key parameters I should take care? How to estimate the amplifier stable? 

 3. Which topology are best solution for high high voltage input? Can I have the details and reasons? Tks. 

Regards,

Xiaobing (Eric)

  • Hi Eric,

    is there any AC content in the input signal?

    Kai
  • In reply to kai klaas69:

    Hi Eric,

    First, I'll link an article that you may find helpful about high voltage measurements. It covers some key points around resistor dividers for high voltages and address your (1) scenario:
    www.eeweb.com/.../considerations-for-high-voltage-measurements

    I would also recommend that you take a look at the circuit cookbook for the differential amplifier and high side current sensing:
    www.ti.com/.../sboa274a.pdf
    www.ti.com/.../sboa310a.pdf
    These documents will help walk through the design procedures and steps you will need to follow.

    For a differential amplifier configuration, you'll have to divide down quite far to get the input signal into the input common mode range of the amplifier. It will be important to consider the input common mode range and offset voltage of the amplifier.

    Regarding stability, that can be simulated and will largely depend on the output load on the amplifier. If you have a large capacitative output, then stability issues will be a concern. I recommend our TIPL videos on stability for how to simulate:
    training.ti.com/ti-precision-labs-op-amps

    I hope this helps get you started. As you work on your circuit, feel free to post back with more questions and a schematic.
    -Paul
  • In reply to kai klaas69:

    Hi Kai,

     Tks for your noted, there is a ripple voltage on DC bus voltage, the frequency around 3-8Khz. Here's power part block diagram for reference. 

  • In reply to Paul Goedeke:

    Hi Kai and Paul,

    Very well, will have that in mind. In application, there is no large capacitance load on Amplifier output. 

    Here is the draft schematic, pls feel free and comments.

    Regards,

    Xiaobing (Eric)

  • In reply to Xiaobing (Eric):

    Hi Eric,

    I threw this circuit into TINA for you to play with. It looks okay to me, the way you have the large resistors makes R1 and R5 sort of irrelevant, the gain is basically 27k/6.12Meg.

    Can you explain why you have a voltage divider on the output? Why not just choose the gain properly have the right output voltage from the op-amp?

    Given this configuration, the considerations laid out in first link of my previous post are very important.

    Best,

    Paul

    TL082_DiffAmp_HighVoltage.TSC

  • In reply to Paul Goedeke:

    Hi Pual,

     Tks for your comments. This circuit have been widely applied in industrial. The voltage divider is not populated in schematic, it's a placeholder. I just have one more concerns, this circuit Gain is below 1, how to  estimate its magnitude margin and phase margin?

     2nd questions, there're voltage sense board failure in customer. As checked the TL082 have low resistance (320R) between negative power (4 pin) and non-inverting input (5 pin). Can you do some comments for possible cause? The circuit show as following:

     Plus, do you have any suggestion for EMI, RFI and protection of Amplifier? Doc. are welcome.  

    Regards,

    Xiaobing (Eric)

  • In reply to Xiaobing (Eric):

    Hi Eric,

    Is the low resistance causing an issue? Does it occur after some time of over-stress event?

    Regarding EMI and protection, take a look at the videos for EOS and ESD:
    EOS: training.ti.com/ti-precision-labs-op-amps
    ESD: training.ti.com/ti-precision-labs-op-amps

    Here is a doc on EMI:
    www.ti.com/.../sboa128a.pdf

    Thanks,
    Paul
  • In reply to Paul Goedeke:

    Hi Paul,

     Tks for your doc, I am enjoying...

     Also for failure analysis, Do you suspect the noise signal inject from OP output side ( R1, 100R)? I'm thinking what's is possible noise route in following block diagram? Can you show me on following diagram? More thanks. 

     

     2. the voltage attenuator's  Gain is below 1, how to estimate its magnitude margin and phase margin? Pls comments. 

    Regards,

    Xiaobing (Eric)

  • In reply to Xiaobing (Eric):

    Hi Eric,

    I recommend a TVS from the output VF1 to signal ground and two clamping diodes directly from pin 7 of U2 to the supply rails. The clamping diodes should not have too much junction capacitiance. Otherwise U2 can become unstable. I usually take the BAV99 or even the BAT54 for this purpose. Eventually, R1 should be a bit increased to better limit the current through the clamping diodes.

    You should also have a TVS from each supply rail to signal ground. Keep an eye on the clamping currents which can eventually flow back into the supply rails. If the voltage regulators cannot accept them, insert blocking diodes.

    Kai

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