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INA240: Output leakage

Guru 40355 points

Replies: 22

Views: 610

Part Number: INA240

The Spice model DC analysis has 49mV output leakage via INN/INP= 0V. The 240 PCB configuration of the Spice model below has the same output leakage violation for very small microvolt +/-INN bias voltage. A single 240 PCB configuration has even more leakage (120mV) than buffered configuration shown here. Very pleased to see 120mV PSRR reduce to 49mV via addition of follower buffer amp but even 49mV seems excessive. The PCB is very flexible for testing various low side configurations of 240 REF inputs in anticipation of possible issues.

How to reduce the output leakage from the 240 output in both the model and PCB configuration?

Actual PCB configuration without R1 installed:

  • Guru 40355 points

    The DC leakage in Spice model CMV 595.99uA, 591.98mV should produce roughly 12mV on 240 output via 2mohm shunt, never 49.59mV. Oddly 49mV is roughly PCB standby leakage captured on scope and the lowest ADC input threshold of the 240 output. Needless to say the minimum digital current measure ADC conversion is roughly 1.1A only during motor deceleration, being SW subtracts leakage threshold for 0A.

  • Guru 40355 points

    In reply to BP101:

    It seems the unedited 240 Spice model disagrees with Fig-2.2 below. Oddly 49mV leakage is not present via REF1/2 = 1.224v and monitor peaks 50 amps 2mohm shunt full ADC. Scope capture even with buffer amp often captures 6v transients, seemingly HF noise since MCU analog comparator threshold is not tripped. Notice VM3 never crosses 0V making it difficult to simulate inductive flyback effecting 240 INP, INN and outputs. Is Fig2-2 fiction ? according model below, positive shunt current INP > INN. Yet the SW or ADC are not inverting the sign from 240 output. So Fig.2-2 is debatably wrong according to Spice transient analysis.

  • In reply to BP101:

    Hi BP101,

    You can try to download the INA240 model again. With input shorted and REF1=REF2=0V, the output should be able to go to as low as 10mV. The online model conservatively set the limit at 30mV. Your sim should show the same if you have the latest model.

    Regards, Guang

  • Guru 40355 points

    In reply to Guang Zhou:

    Hi Guang,

    Notice I continue the Fig.2-2 inversion issue from other thread. Again I test REF mid supply configuration versus REF=GND and 240 error % grows large.  Precision SW check Min/Max to extract True RMS (0.707) peak values from pulsed wave form only correctly works REF=GND.

    The other issue being REF mid supply (+1.224v) PSRR/CMRR may allow spurious shunt transients into output waveform. False trip of comparator threshold does not occur via REF=GND, analog fault comparators in MCU do not falsely trip, threshold set 1.39v. Yet when REF=1.224v or mid supply (1.65v) and set MAX fault trip point (>3.1v) every little fault trip occur in 50 amp full scale. The connection to make being PWM rejection is somehow greatly effected by REF pin set above GND and 240 precision suffers as a result. Why is that not shown in datasheet CMRR/PSRR graphs as it seems the rejection decibel level is being effected by REF input?

    That is why Fig.2.2 inversion seems to occur in 240 output and REF=GND produces the highest precision possible with maintaining PWM transient rejection. So TI example TIDA-00909 set 240 REF mid supply (+1.65v) seems off track for any measure >16 amps full scale. It also hides PSRR/CMRR and REF input is effecting PWM rejection of shunt transients migration past the internal input filter.

    Perhaps TI can explain or evaluate why REF set mid supply allow PWM transients to migrate into 240 output but not when REF=GND and how each configuration of REF effects error % precision?

  • In reply to BP101:

    Hi BP101,

    From INA240’s perspective, the magnitude of the current makes no difference. What it senses is the differential voltage that the current develops over the shunt.

    As long as the output is not limited, it doesn’t matter how REF is connected, the PSRR and CMRR shouldn’t change drastically. If you observe otherwise, something else is going on. The best way to eliminate your doubt is to test the IC itself other than in a system. 

    TIDA909 employs bidirectional sensing by necessity not by choice. Even in low side sensing, the amplifier normally should be configured in bidirectional mode. When configured in unidirectional mode, you’re clipping its output at ground if in reality it should be below. The phase current can be negative, or flowing from ground up through the FET into motor windings, it is not fictional.

    Regards, Guang

  • Guru 40355 points

    In reply to Guang Zhou:

    Hi Guang,

    First the updated 240 model I download is only little better (29mV) leakage and the second 240 worse (36mV_ via DC analysis. Realistic circuit has about 20-30mV of leakage on second 240 and did not help to reduce transients from the mid REF configuration of first 240.

    Guang Zhou
    When configured in unidirectional mode, you’re clipping its output at ground if in reality it should be below

    Seemingly we don't need to measure the faster PWM 80us switching in Fig2-2, rather the Slower AC inductive current occurring above ground. Oddly when REF1,2 are mid supply (+1.224 to +1.65v) 240 produces incorrect Peak current measures. Again compared to external 100 amp bar ground side, 240 output slower slew rate reduces ADC charge share peaks and falls behind true RMS "Only from mid REF."

    The scope capture is significantly different in the 240 output slew rate that occurs from mid REF being much slower than it is from ground REF. Seemingly slew rate is somehow effected by the REF pins configuration being set above ground. The RMS digital value of ADC from setting mid REF falls far behind from where it should compared to True RMS DMM or other external measures. Perhaps slower output slew rate (Mid REF) explains why the analog comparators trip point is so easily reached and not at all from REF=GND?

    How can we increase output slew rate for Mid REF so 240 produces the same magnitude signal as REF from ground? Single ended ADC charge share is not the same (Mid REF) as the input never fully discharges CADC every 1.3ms. Not that should be a problem if the output slew rate remains constant no mater how REF is being configured.

    The transients that pass through the 240 output from Mid REF are a game stopper for low side monitor. The MCU three analog comparators threshold does not lie!

  • In reply to BP101:

    Hi BP101,

    How ref pins are connected shouldn’t affect output slew rate. Do you have side by side scope plots that compare the too situations? Preferably show them under identical conditions with REF being the only difference. Also if you can indicate the location where the comparators are tripped, it would be good information.

    Regards, Guang

  • Guru 40355 points

    In reply to Guang Zhou:

    Hi Guang,

    I provided both REF captures in the related forum post to this one and past posts.  I get that SW (mid REF) must subtract +1.224v difference to compensate the ADC samples. The observation part being the rate of attack obviously slows for <1/2 REF VS, that is slew rate in my book.  Again <1/2 (mid REF) configuration produce higher magnitude transients in the slower slew rate. Seemingly reduced slew rate is why <1/2 mid REF configuration via precision reference (1.224v) produces a very small window (<5A) compared to when REF=GND or exactly set 1/2 VS (1.65v)?

    Oddly Spice model in this thread is not producing negative shunt CM shown in (Fig 2-2), even 100% PWM duty cycle no matter how REF is configured.  

    The slew rate is not exactly noted by transient response graphs, Figs. 21-22 set 1/2 VS. Perhaps slew rate changes for REF configured <1/2 VS supply? Note datasheet does not show testing graphs for REF pins configured < 1/2 VS, though text 8.4.3.1 contradicts Figure 28 and REF=2.5v is not shown as text states.

    8.4.3.1 Output Set to External Reference Voltage:

    Connecting both pins together and then to a reference voltage results in an output voltage equal to the reference voltage for the condition of shorted input pins or a 0-V differential input; this configuration is shown in Figure 28. The output voltage decreases below the reference voltage when the IN+ pin is negative relative to the IN– pin and increases when the IN+ pin is positive relative to the IN– pin. This technique is the most accurate way to bias the output to a precise voltage.

  • Guru 40355 points

    In reply to BP101:

    BP101
    8.4.3.1 Output Set to External Reference Voltage

    Contradicting text and Fig. 28 do not provide any evidence the differential amplifier output slew rate is not significantly being changed from 1.224v REF <1/2 (1.65v), VS (3.3v). That is the only deductive explanation why MCU analog comparators are so easily tripped. No comparator Fault trips for +1.39v threshold (REF=GND) versus >3.1v threshold simply adding +1.224v (mid REF) to the output, confirms 8.4.3.1 is not so factual!

    If anything the trip threshold 1.39v + 1.224v = 2.614v, NOT >3.1v - that is just below 50A FULL scale. Any way the motor does not require that much startup current at 165VDC. So the 240 is not producing correct results <1/2 mid REF for what ever reason. The point of reporting is for TI to fix the issue or change the datasheet so others do not fall victim to very same mayhem.

  • In reply to BP101:

    Hi BP101,

    I highly doubt the slew rate is going to be influenced by the reference pin potential, but I’ll verify it as soon as I get a chance in the next couple of days.

    Thank you for your best intention, if indeed there is anything that should be reflected in the datasheet, we’ll definitely do so.

    Regards, Guang

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