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THS4031: Asymmetrical biasing of THS4031 (5962-9959501Q2A)

Part Number: THS4031

Hello;
I am wondering that whether I can or can not set the bias for THS4031 (5962-9959501Q2A) as +5V and -3.3V?
There are two issues here:
1) Asymmetrical voltages. One is 3.3 and the other is 5.
2) The potential difference is less than 9V, which is unclear in the datasheet.

Regards,
Sinan ONAT

  • Hi Sinan,

    Do you mean set Vcc+ = +5V and Vcc- = -3.3V? While there is no issue in asymmetrical supply voltages, as long as your input signal is properly referenced and kept around mid common-mode range, having a potential difference of less than 9V for the supply voltage is below the Recommended Operating Conditions in 7.3.

    Best regards,

    Sean
  • Hello Sean;

    Yes, I meant that setting. And my Vreference+ is equal to 1.4V, while my Vref- is fed by the charge pump as stated below. The problem below (1030 MHz PLL)  is, somehow the output of your op-amp is always very close to Vcc+. I do not get why and how it is stuck to around the highest supply voltage immediately. To be more specific, it is 3.9V, which is very similar to the "output voltage swing" specification (for 1 k-ohm) in the datasheet.  

    And this fact is consistent with my other (1090 MHz) PLL. Below, the Vcc+ is +10V, Vcc- is 0V (GND), Vref+: 3.9V and Vref- is fed by charge pump. However, again the output of the op-amp is immediately set to 9V, which is again very close to the Vcc+ of op-amp.

    Here the supply voltage of both VCO (MFC102110-5) and PFD (ADF4106) are +5V. And the operating voltage range of the VCO is between 0V and 5V. Therefore I believe I have a problem with using op-amp, although it is a very simple PLL circuitry suggested by the PLL design software. I truly do not want to change my op-amp but please advise me for successfully operating op-amp to avoid it is being stuck to the high side.

    Regards,

    Sinan

  • Hi Sinan,

    Even though you are using inverting gain for the signal, the Vref itself is still in non-inverting gain. In the 1090MHz case above, Vref=3.9V and it is sees a DC gain of 1+Rf/Rg=1+1.2k/100=13V/V. Since 13*3.9 is above the output limitation, it is clipped. To center your output around 3.9V, use 3.9/13= 0.3V as your Vref. Is there any reason you aren't centering it around mid supply (5V)?

    Best regards,

    Sean
  • Hello Sean;
    Thank you for your advise.
    For the first (top most) circuit for 1030 MHz PLL, my voltages are as follows: Vcc+ = +5V, Vcc- = -5V, Vref+ = 0.95V (after your suggestion referring to the formula above). In the second (below) circuit for 1090 MHz PLL, the voltages are: Vcc+ = +10V, Vcc- = 0V, Vref+ = 0.3V (after your suggestion referring to the formula above).
    Unfortunately, I observe a strange thing here. The current consumption of the op-amp from the Vref+ pin is huge (0.5A for 0.3V, asking more than 1A for 0.95V), which is not what I was expecting. Why is that? Is the IC broken?

    Truthfully, I did not have any preference on setting Vref to any voltage as long as it is in the range between 1V neighborhood of the supply voltages. However this current consumption issue worries me. I believe there is something wrong, please advise me.
    Regards,
    Sinan
  • I found the over current problem, it was due to a broken (short) connection to ground.
    But my question on 1030 MHz and 1090 MHz PLL circuit reference voltages are still valid, would you please confirm that?
    Indeed, they are too low for me to set. I would rather set Vref+ to 1.5V instead.
  • Hello Sean;

    The DC gain you stated does not apply to integrator configuration where RF is serially connected to the capacitor (C2). We try to use the op-amp as an integrator. The op-amp amplifies with full open loop DC gain.

    Our most recent problem is, V+ input (connected to Vref) tracks V- input for input voltages V- input greater than V+ input. For example, if we set V+ input to 1V, and when we program the PLL, V- input swings from 1.6V to Vsupply+ (+5V) and V+ input is pulled up to 1.6V. This should never happen, what drives the op-amp? V+ input is connected to low impedance Power Supply (as Vref).

    Regards,

    Sinan

  • Hi Sinan,

    It seems to me that without any DC feedback path, the feedback capacitors would charge up until the amplifier rails out. I would try attaching a 10k resistor across the feedback circuit and see if it helps.

    Since you are designing a PLL, why are you using the amplifier as integrator instead of a LPF? The purpose of the PLL is to synchronize input and output frequency by adjusting the output frequency proportionally to the input and output phase difference. Since the oscillator is voltage controlled, it needs to be controlled by a voltage proportional to the phase difference. In my understanding, the purpose of the phase detector is to mix the input A(t)=A*cos(wot+Φa) and the output B(t)=B*cos(wot+Φb) into A(t)*B(t)=(AB/2)*(cos(2wot+Φa+Φb)+cos(Φa-Φb)). Then the LPF filters out the 2nd order harmonic and leaves the phase proportional (AB/2)*cos(Φa-Φb) term. If you simply require the amplifier to provide gain, you could configure it with the needed resistors and put a low pass RC filter on the output.

    What is the settling time you are aiming for?

    Best regards,

    Sean
  • Hi Sinan,

    I understand now why you need an integrator. This is a mixed signal PLL where the charge pump produces a PWM signal proportional to the phase error. The active PLL loop filter circuits you are using are called true-time integrators, which only work when the loop is perfectly balanced. Adding the parallel resistor mentioned above will counteract DC errors like Vos and Ib from integrating until the feedback capacitors charge to the rail. You may need to try a few values to balance between DC compensation and integrator ideality. If it is too low it will start to load your charge pump as well. The Vref value should be half your charge pump voltage, and should be very clean, using a low noise linear regulator or a low resistance voltage divider with a coupling capacitor near the V+ pin.

    Best regards,

    Sean